summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
diff options
context:
space:
mode:
authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-01-14 21:59:22 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-01-14 21:59:22 +0000
commit0d11212f004c9193dd1cb2b01a80d6934b5fb5f9 (patch)
tree986c25e8fbf9c50e753d7cf977f947191ae7b71e /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
parent80c0974c6bc690f7087693f1704747e664d06d1a (diff)
downloadbcm5719-llvm-0d11212f004c9193dd1cb2b01a80d6934b5fb5f9.tar.gz
bcm5719-llvm-0d11212f004c9193dd1cb2b01a80d6934b5fb5f9.zip
[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
llvm-svn: 257815
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index ab28120ba27..8ded94d062a 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1966,11 +1966,10 @@ bool BitSimplification::genExtractHalf(MachineInstr *MI,
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
.addReg(L.Reg, 0, L.Sub);
- } else if (!L.Low && Opc != Hexagon::S2_extractu) {
+ } else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
- BuildMI(B, MI, DL, HII.get(Hexagon::S2_extractu), NewR)
+ BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
.addReg(L.Reg, 0, L.Sub)
- .addImm(16)
.addImm(16);
}
if (NewR == 0)
OpenPOWER on IntegriCloud