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authorBenjamin Kramer <benny.kra@googlemail.com>2016-06-12 17:30:47 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2016-06-12 17:30:47 +0000
commit4ca41fd09ed05286a22661b865a6ec5728a58d08 (patch)
tree8a1cbce4cbc754c1e1793ba0685fab3a42c4f165 /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
parentb17b9a8324763a563bc03eafc8446fcf4c702491 (diff)
downloadbcm5719-llvm-4ca41fd09ed05286a22661b865a6ec5728a58d08.tar.gz
bcm5719-llvm-4ca41fd09ed05286a22661b865a6ec5728a58d08.zip
Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.
No functionality change intended. llvm-svn: 272516
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index a6a9e33dd17..d69554f95f9 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1302,7 +1302,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
continue;
// If found, replace the instruction with a COPY.
- DebugLoc DL = MI->getDebugLoc();
+ const DebugLoc &DL = MI->getDebugLoc();
const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
unsigned NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
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