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path: root/llvm/lib/Target/Hexagon/Hexagon.td
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-051-1/+1
* [Hexagon] Foundation of support for Hexagon V66Krzysztof Parzyszek2018-12-051-2/+17
* [Hexagon] Switch to auto-generated intrinsic definitions and patternsKrzysztof Parzyszek2018-12-031-2/+0
* [Hexagon] Implement noreturn optimizationBrendon Cahoon2018-11-091-0/+3
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-11/+7
* [Hexagon] Add a "generic" cpuBrendon Cahoon2018-06-261-0/+4
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-151-1/+0
* [Hexagon] Add a target feature to control using small data sectionKrzysztof Parzyszek2018-05-141-6/+8
* [Hexagon] Add a target feature for generating new-value storesKrzysztof Parzyszek2018-05-141-6/+13
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-10/+15
* [Hexagon] Remove -mhvx-double and the corresponding subtarget featureKrzysztof Parzyszek2018-04-031-18/+9
* [Hexagon] Subtarget feature to emit one instruction per packetKrzysztof Parzyszek2018-03-121-6/+13
* [Hexagon] Implement target feature +reserved-r19Krzysztof Parzyszek2018-02-281-0/+2
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-091-0/+1
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-061-0/+1
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-22/+55
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-1/+0
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-181-14/+42
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-051-13/+13
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-0/+3
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-101-0/+3
* [Hexagon] Remove unused .td filesKrzysztof Parzyszek2017-02-101-1/+0
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-13/+13
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-061-5/+5
* [Hexagon] Adding additional tokenization characters in preparation for removi...Colin LeMahieu2016-12-051-1/+1
* [Hexagon] Split all selection patterns into a separate fileKrzysztof Parzyszek2016-11-051-0/+1
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-8/+9
* [Hexagon] Merge HexagonAlias.td into HexagonInstrAlias.td, NFCKrzysztof Parzyszek2016-05-051-1/+0
* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-291-1/+25
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-281-0/+1
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-211-0/+1
* [TableGen] Modify the AsmMatcherEmitter to only apply the table growth from r...Craig Topper2015-12-311-0/+5
* [Hexagon] Subtarget features/default CPU correctionsKrzysztof Parzyszek2015-12-141-1/+1
* [Hexagon] Hexagon V60 HVX intrinsic defintionsKrzysztof Parzyszek2015-11-261-1/+1
* [Hexagon] Bring HexagonInstrInfo up to dateKrzysztof Parzyszek2015-11-241-0/+36
* [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction pars...Colin LeMahieu2015-11-091-0/+9
* [Hexagon] Change Based->Base in getBasedWithImmOffsetKrzysztof Parzyszek2015-10-201-1/+1
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-201-1/+1
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-171-9/+24
* Make the Hexagon ISelDAGToDAG pass set the subtarget dynamicallyEric Christopher2015-03-211-4/+4
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-121-4/+4
* Hexagon: Remove unused InstrMapping.Benjamin Kramer2015-03-101-8/+0
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-091-19/+7
* Migrate HexagonISelDAGToDAG to setting a subtarget pointer duringEric Christopher2015-02-021-12/+12
* [Hexagon] Adding dealloc_return encoding and absolute address stores.Colin LeMahieu2015-01-061-2/+2
* [Hexagon] Adding reg-reg indexed load forms.Colin LeMahieu2014-12-301-0/+10
* [Hexagon] Add new InstrItinClass to support timing classes.Jyotsna Verma2014-05-081-2/+0
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-021-10/+0
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