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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-051-1/+1
| | | | llvm-svn: 348411
* [Hexagon] Foundation of support for Hexagon V66Krzysztof Parzyszek2018-12-051-2/+17
| | | | llvm-svn: 348407
* [Hexagon] Switch to auto-generated intrinsic definitions and patternsKrzysztof Parzyszek2018-12-031-2/+0
| | | | llvm-svn: 348206
* [Hexagon] Implement noreturn optimizationBrendon Cahoon2018-11-091-0/+3
| | | | | | | | | | | Eliminate the stack frame in functions with the noreturn nounwind attributes, and when the noreturn-stack-elim target feature is enabled. This reduces the code and stack space needed for noreturn functions. Differential Revision: https://reviews.llvm.org/D54210 llvm-svn: 346532
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-11/+7
| | | | llvm-svn: 344791
* [Hexagon] Add a "generic" cpuBrendon Cahoon2018-06-261-0/+4
| | | | | | | | | | Add the generic processor for Hexagon so that it can be used with 3rd party programs that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon. Differential Revision: https://reviews.llvm.org/D48571 llvm-svn: 335641
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-151-1/+0
| | | | llvm-svn: 332365
* [Hexagon] Add a target feature to control using small data sectionKrzysztof Parzyszek2018-05-141-6/+8
| | | | llvm-svn: 332292
* [Hexagon] Add a target feature for generating new-value storesKrzysztof Parzyszek2018-05-141-6/+13
| | | | llvm-svn: 332290
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-10/+15
| | | | llvm-svn: 332285
* [Hexagon] Remove -mhvx-double and the corresponding subtarget featureKrzysztof Parzyszek2018-04-031-18/+9
| | | | | | | Specifying the HVX vector length should be done via the -mhvx-length option. llvm-svn: 329079
* [Hexagon] Subtarget feature to emit one instruction per packetKrzysztof Parzyszek2018-03-121-6/+13
| | | | | | | | | | | | | | | | | This adds two features: "packets", and "nvj". Enabling "packets" allows the compiler to generate instruction packets, while disabling it will prevent it and disable all optimizations that generate them. This feature is enabled by default on all subtargets. The feature "nvj" allows the compiler to generate new-value jumps and it implies "packets". It is enabled on all subtargets. The exception is made for packets with endloop instructions, since they require a certain minimum number of instructions in the packets to which they apply. Disabling "packets" will not prevent hardware loops from being generated. llvm-svn: 327302
* [Hexagon] Implement target feature +reserved-r19Krzysztof Parzyszek2018-02-281-0/+2
| | | | llvm-svn: 326364
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [Hexagon] Express calling conventions via .td file instead of hand-codingKrzysztof Parzyszek2018-02-091-0/+1
| | | | | | Additionally, simplify the rest of the argument/parameter lowering code. llvm-svn: 324737
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-061-0/+1
| | | | llvm-svn: 324392
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-22/+55
| | | | llvm-svn: 320404
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-1/+0
| | | | llvm-svn: 316228
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-181-14/+42
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Give uniform names to functions changing addressing modes, NFCKrzysztof Parzyszek2017-10-051-13/+13
| | | | | | | | | | | | | | | The new format is changeAddrMode_xx_yy, where xx is the current mode, and yy is the new one. Old name: New name: getBaseWithImmOffset changeAddrMode_abs_io getAbsoluteForm changeAddrMode_io_abs getBaseWithRegOffset changeAddrMode_io_rr xformRegToImmOffset changeAddrMode_rr_io getBaseWithLongOffset changeAddrMode_rr_ur getRegShlForm changeAddrMode_ur_rr llvm-svn: 315013
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-0/+3
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-101-0/+3
| | | | llvm-svn: 294805
* [Hexagon] Remove unused .td filesKrzysztof Parzyszek2017-02-101-1/+0
| | | | llvm-svn: 294775
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-13/+13
| | | | llvm-svn: 294753
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-061-5/+5
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* [Hexagon] Adding additional tokenization characters in preparation for ↵Colin LeMahieu2016-12-051-1/+1
| | | | | | removing spacing from syntax. llvm-svn: 288637
* [Hexagon] Split all selection patterns into a separate fileKrzysztof Parzyszek2016-11-051-0/+1
| | | | | | | This is just the basic separation, without any cleanup. Further changes will follow. llvm-svn: 286036
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-8/+9
| | | | llvm-svn: 276638
* [Hexagon] Merge HexagonAlias.td into HexagonInstrAlias.td, NFCKrzysztof Parzyszek2016-05-051-1/+0
| | | | llvm-svn: 268641
* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-291-1/+25
| | | | | | Patch by Jyotsna Verma. llvm-svn: 268051
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-281-0/+1
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-211-0/+1
| | | | llvm-svn: 267038
* [TableGen] Modify the AsmMatcherEmitter to only apply the table growth from ↵Craig Topper2015-12-311-0/+5
| | | | | | | | | | | | | | r252440 to the Hexagon target. This restores the previous behavior of not including the mnemonic in the classes table for every target that starts instruction lines with the mnemonic. Not only did the table size increase by 1 entry, but the class enum increased in size which caused every class in the array to increase in size. It also grew the size of the function that parsers tokens into classes by a substantial amount. This adds a new HasMnemonicFirst flag to all AsmParsers. It's set to 1 by default and Hexagon target overrides it to 0. For the X86 target alone this recovers 324KB of size on the llvm-mc executable. I believe the current state is still a bad design choice for the Hexagon target as it causes most of the parsing to do a linear search through the entire match table to comparing operands against every instruction until it finds one that works. At least for the other targets we do a binary search based on mnemonic over which to do the linear scan. llvm-svn: 256669
* [Hexagon] Subtarget features/default CPU correctionsKrzysztof Parzyszek2015-12-141-1/+1
| | | | llvm-svn: 255501
* [Hexagon] Hexagon V60 HVX intrinsic defintionsKrzysztof Parzyszek2015-11-261-1/+1
| | | | | Author: Ron Lieberman <ronl@codeaurora.org> llvm-svn: 254165
* [Hexagon] Bring HexagonInstrInfo up to dateKrzysztof Parzyszek2015-11-241-0/+36
| | | | llvm-svn: 253986
* [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction ↵Colin LeMahieu2015-11-091-0/+9
| | | | | | parsing tests. General updating of the code emission. llvm-svn: 252443
* [Hexagon] Change Based->Base in getBasedWithImmOffsetKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250848
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250845
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-171-9/+24
| | | | llvm-svn: 250600
* Make the Hexagon ISelDAGToDAG pass set the subtarget dynamicallyEric Christopher2015-03-211-4/+4
| | | | | | on each runOnMachineFunction invocation. llvm-svn: 232874
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-121-4/+4
| | | | llvm-svn: 232057
* Hexagon: Remove unused InstrMapping.Benjamin Kramer2015-03-101-8/+0
| | | | llvm-svn: 231809
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-091-19/+7
| | | | llvm-svn: 228614
* Migrate HexagonISelDAGToDAG to setting a subtarget pointer duringEric Christopher2015-02-021-12/+12
| | | | | | runOnMachineFunction. Update all uses of the Subtarget accordingly. llvm-svn: 227840
* [Hexagon] Adding dealloc_return encoding and absolute address stores.Colin LeMahieu2015-01-061-2/+2
| | | | llvm-svn: 225267
* [Hexagon] Adding reg-reg indexed load forms.Colin LeMahieu2014-12-301-0/+10
| | | | llvm-svn: 224997
* [Hexagon] Add new InstrItinClass to support timing classes.Jyotsna Verma2014-05-081-2/+0
| | | | | | | This patch doesn't introduce any functionality change. Test cases will be added later when v5 support is added. llvm-svn: 208349
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-021-10/+0
| | | | llvm-svn: 196065
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