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path: root/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp
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* Remove the CellSPU port.Eric Christopher2012-11-141-333/+0
| | | | | | Approved by Chris Lattner. llvm-svn: 167984
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-4/+2
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Add branch hinting for SPU. Kalle Raiskila2011-02-281-0/+7
| | | | | | | The implemented algorithm is overly simplistic (just speculate all branches are taken)- this is work in progress. llvm-svn: 126651
* move all the target's asmprinters into the main target. The piece Chris Lattner2010-11-141-0/+327
| | | | | | | that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
* CellSPU:Scott Michel2008-11-201-0/+0
| | | | | | | | (a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy. (b) Remove truncated stores that will never be used. (c) Add initial support for __muldi3 as a libcall. llvm-svn: 59734
* CellSPU: Bring SPU's assembly printer more in-line with current LLVM codeScott Michel2008-11-081-645/+0
| | | | | | structure. Assembly printer now outputs the correct section for strings. llvm-svn: 58921
* Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stackScott Michel2008-10-301-2/+4
| | | | | | | | | so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU. N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is still unexorcised code. llvm-svn: 58415
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-12/+12
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* If we have a function with an unreachable statement such that the ending debugBill Wendling2008-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information is in an unreachable block, then it's possible that the high/low pc values won't be set for the dwarf information. E.g., this function: void abort(void) __attribute__((__noreturn__)); void dead_beef(void) __attribute__ ((noreturn)); int *b; void dead_beef(void) { *b=0xdeadbeef; abort(); } has a call to "@llvm.dbg.region.end" only in the unreachable block: define void @dead_beef() noreturn nounwind { entry: call void @llvm.dbg.func.start(...) call void @llvm.dbg.stoppoint(...) ... call void @abort( ) noreturn nounwind unreachable return: ; No predecessors! call void @llvm.dbg.stoppoint(...) call void @llvm.dbg.region.end(...) ret void } The dwarf information emitted is something like: 0x00000084: TAG_subprogram [5] AT_name( "dead_beef" ) AT_external( 0x01 ) AT_prototyped( 0x01 ) AT_decl_file( 0x01 ) AT_decl_line( 0x08 ) Note that this is *not* the best fix for this problem, but a band-aid for an gaping wound. This code needs to be changed when we revamp our debugging information. llvm-svn: 56628
* Move actual section printing stuff to AsmPrinter from TAI reducing heap traffic.Anton Korobeynikov2008-09-241-1/+1
| | | | llvm-svn: 56573
* Drop obsolete hook and change all usage to new interfaceAnton Korobeynikov2008-09-241-17/+1
| | | | llvm-svn: 56572
* SPU section handling is really huge mess. Replace remaining TAI calls for ↵Anton Korobeynikov2008-09-241-2/+2
| | | | | | sections with explicit names in order not to block existing backends during section handling migration. SPU folks! Please consider using new section handling facility someday. llvm-svn: 56570
* Use raw_ostream throughout the AsmPrinter.Owen Anderson2008-08-211-3/+4
| | | | llvm-svn: 55092
* Emit debug info for data-only files on Cell SPU.Dale Johannesen2008-07-091-3/+5
| | | | | | I cannot test this target, let me know if it breaks! llvm-svn: 53363
* Add CommonLinkage; currently tentative definitionsDale Johannesen2008-05-141-2/+3
| | | | | | | | | | are represented as "weak", but there are subtle differences in some cases on Darwin, so we need both. The intent is that "common" will behave identically to "weak" unless somebody changes their target to do something else. No functional change as yet. llvm-svn: 51118
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-1/+1
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-3/+3
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-3/+4
| | | | llvm-svn: 46930
* Get rid of the annoying blank lines before labels.Evan Cheng2008-02-021-1/+0
| | | | llvm-svn: 46667
* More cleanups for CellSPU:Scott Michel2008-01-301-5/+5
| | | | | | | | | - Expand tabs... (poss 80-col violations, will get them later...) - Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single function, simplifying maintenance. Also reduced custom instruction generation for SPUvecinsert/INSERT_MASK. llvm-svn: 46544
* Overhaul Cell SPU's addressing mode internals so that there are nowScott Michel2008-01-291-4/+10
| | | | | | | | | | | | | | only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. llvm-svn: 46483
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-3/+3
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-14/+14
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-6/+2
| | | | llvm-svn: 45418
* More working CellSPU tests:Scott Michel2007-12-201-1/+1
| | | | | | | - vec_const.ll: Vector constant loads - immed64.ll: i64, f64 constant loads llvm-svn: 45242
* Updated source file headers to llvm coding standard.Scott Michel2007-12-051-3/+2
| | | | llvm-svn: 44597
* More of the Cell SPU code drop from "Team Aerospace".Scott Michel2007-12-041-0/+654
llvm-svn: 44582
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