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* Kill some dead code.Jim Grosbach2011-05-161-3/+1
| | | | llvm-svn: 131431
* sets bit 0 of the function address of thumb function in .symtabRafael Espindola2011-05-162-6/+21
| | | | | | | | | | ("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! llvm-svn: 131406
* Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.Owen Anderson2011-05-111-4/+8
| | | | llvm-svn: 131189
* Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmpBill Wendling2011-05-112-4/+4
| | | | | | | | intrinsic call. This prevents it from being reordered so that it appears *before* the setjmp intrinsic (thus making it completely useless). <rdar://problem/9409683> llvm-svn: 131174
* First cut at getting debugging support for ARM/MC/ELF/.oJason W Kim2011-05-101-1/+0
| | | | | | | DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(), but the offset is not guaranteed to be mod 4 == 0 as in text/data. llvm-svn: 131137
* Fixed MC encoding for index_align for VLD1/VST1 (single element from one ↵Mon P Wang2011-05-094-2/+60
| | | | | | lane) for size 32 llvm-svn: 131085
* Eliminate the ARM sub-register indexes that are not needed by the sources.Jakob Stoklund Olesen2011-05-071-33/+6
| | | | | | | Tablegen will invent its own names for these indexes, and the register file is a bit simpler. llvm-svn: 131059
* Fix the non-MC encoding of pkhbt and pkhtb.Eric Christopher2011-05-071-0/+6
| | | | | | Patch by Stephen Hines. llvm-svn: 131045
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-062-8/+2
| | | | | | functionality change. llvm-svn: 131012
* Dead code elimination.Rafael Espindola2011-05-061-2/+0
| | | | llvm-svn: 130984
* Do not emit location expression size twice.Devang Patel2011-05-041-12/+0
| | | | llvm-svn: 130854
* Mark ultra-super-registers QQQQ as call-clobbered instead of the D ↵Jakob Stoklund Olesen2011-05-033-32/+11
| | | | | | | | | | | | | | | sub-registers. LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites Q0, so if Q0 is live-in to a function, its live range will extend beyond a function call that only clobbers D0 and D1. This shows up in the ARM/2009-11-01-NeonMoves test case. LiveVariables should probably implement the much stricter rules for physreg liveness that RAFast imposes - a physreg is killed by the first use of any alias. llvm-svn: 130801
* Temporarily disable use of divmod compiler-rt functions for iOS.Bob Wilson2011-05-031-6/+0
| | | | llvm-svn: 130766
* Fold ARM coprocessor intrinsics patterns into the instructions defs wheneverBruno Cardoso Lopes2011-05-033-96/+73
| | | | | | it's possible. llvm-svn: 130764
* Add a few ARM coprocessor intrinsics. Testcases includedBruno Cardoso Lopes2011-05-034-0/+71
| | | | llvm-svn: 130763
* Add an unfolded offset field to LSR's Formula record. This is used toDan Gohman2011-05-032-0/+14
| | | | | | | | model constants which can be added to base registers via add-immediate instructions which don't require an additional register to materialize the immediate. llvm-svn: 130743
* Apparently the check for direct calls is unnecessary.Eric Christopher2011-05-021-2/+2
| | | | llvm-svn: 130716
* 80-col.Eric Christopher2011-04-291-8/+9
| | | | llvm-svn: 130558
* Zap a couple now-unused functions.Eli Friedman2011-04-291-10/+0
| | | | llvm-svn: 130557
* Switch to ImmLeaf (which can be used by FastISel) for a few more common ↵Eli Friedman2011-04-293-2/+7
| | | | | | ARM/Thumb2 patterns. llvm-svn: 130552
* Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, butEric Christopher2011-04-291-0/+23
| | | | | | if it ever did it needs the def machinery. llvm-svn: 130549
* Some cleanup and optimize fallthrough more.Eric Christopher2011-04-291-8/+13
| | | | llvm-svn: 130546
* Re-committing r130454, which does not in fact break anything.Eli Friedman2011-04-291-19/+2
| | | | | | | Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. rdar://problem/9338332 . llvm-svn: 130539
* Add trunc->branch support, this won't help with clang's i8->i1 truncationsEric Christopher2011-04-291-1/+24
| | | | | | for bools, but is a start. llvm-svn: 130534
* MCExpr: Add FindAssociatedSection, which attempts to mirror the 'as' semanticsDaniel Dunbar2011-04-291-0/+3
| | | | | | that associate sections with expressions. llvm-svn: 130517
* Teach Thumb2 isel to fold and->rotr ==> ROR.Andrew Trick2011-04-291-0/+9
| | | | | | Generalization of Nate Begeman's patch! llvm-svn: 130502
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-294-21/+18
| | | | | | There are probably more instances of this floating around. llvm-svn: 130474
* Update comments and checks to match reality.Eric Christopher2011-04-291-9/+2
| | | | llvm-svn: 130464
* Whitespace.Eric Christopher2011-04-291-11/+11
| | | | llvm-svn: 130463
* Revert r130454; apparently this doesn't actually work.Eli Friedman2011-04-281-2/+19
| | | | llvm-svn: 130462
* Fix a rather obscure crash caused by ARM fast-isel generating code which ↵Eli Friedman2011-04-281-19/+2
| | | | | | | | redefines a register. rdar://problem/9338332 . llvm-svn: 130454
* Be more layout aware here and swap the successor and branch conditionEric Christopher2011-04-281-1/+8
| | | | | | if it means we get a fallthrough. llvm-svn: 130404
* Let the immediate leaf pattern take transforms and switch the signedEric Christopher2011-04-283-30/+30
| | | | | | | | immediate patterns in arm to using the pattern. Handles rdar://9299434 llvm-svn: 130386
* Teach dwarf writer to handle complex address expression for .debug_loc entries.Devang Patel2011-04-282-0/+45
| | | | | | | This fixes clang generated blocks' variables' debug info. Radar 9279956. llvm-svn: 130373
* Fix a bug in the case that there is no add or subtract symbol and the offsetKevin Enderby2011-04-271-2/+6
| | | | | | value is zero so it does not add a NULL expr operand. llvm-svn: 130330
* Revert r130178. It turned out to be not the optimal path to emit complex ↵Devang Patel2011-04-272-8/+5
| | | | | | location expressions. llvm-svn: 130326
* ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads.Jim Grosbach2011-04-263-0/+184
| | | | | | rdar://9326019 llvm-svn: 130234
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on ↵Jakob Stoklund Olesen2011-04-264-0/+33
| | | | | | | | | | | | register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. llvm-svn: 130228
* Let dwarf writer allocate extra space in the debug location expression. This ↵Devang Patel2011-04-262-5/+8
| | | | | | space, if requested, will be used for complex addresses of the Blocks' variables. llvm-svn: 130178
* Fix Target/ARM/Thumb1FrameLowering.h header guard.Sebastian Redl2011-04-241-1/+1
| | | | llvm-svn: 130097
* Thumb2 and ARM add/subtract with carry fixes.Andrew Trick2011-04-234-115/+106
| | | | | | | | | | | | | Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). llvm-svn: 130048
* whitespaceAndrew Trick2011-04-231-6/+6
| | | | llvm-svn: 130046
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+13
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Add asserts.Devang Patel2011-04-221-0/+2
| | | | llvm-svn: 129995
* In Thumb2 mode, lower frame indix references to:Evan Cheng2011-04-222-9/+13
| | | | | | | | | | | add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 llvm-svn: 129971
* Fix DWARF description of Q registers.Devang Patel2011-04-211-0/+27
| | | | llvm-svn: 129952
* Fix DWARF description of S registers.Devang Patel2011-04-212-0/+44
| | | | llvm-svn: 129947
* As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF.Devang Patel2011-04-211-24/+32
| | | | llvm-svn: 129922
* Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng2011-04-202-1/+4
| | | | llvm-svn: 129884
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-0/+3
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
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