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| author | Devang Patel <dpatel@apple.com> | 2011-05-04 19:00:57 +0000 |
|---|---|---|
| committer | Devang Patel <dpatel@apple.com> | 2011-05-04 19:00:57 +0000 |
| commit | 39ecf816c5119b5734b7344939d1f62cae7598f9 (patch) | |
| tree | 8ba3e93103cbcbe0fbd2a6e99913ecd4a3a6620c /llvm/lib/Target/ARM | |
| parent | 9d82fea37803e9f917f730487fe606db1a320fb6 (diff) | |
| download | bcm5719-llvm-39ecf816c5119b5734b7344939d1f62cae7598f9.tar.gz bcm5719-llvm-39ecf816c5119b5734b7344939d1f62cae7598f9.zip | |
Do not emit location expression size twice.
llvm-svn: 130854
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index c428e1852a4..f90d3756b37 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -188,7 +188,6 @@ unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const { unsigned SReg = Reg - ARM::S0; unsigned Rx = 256 + (SReg >> 1); - OutStreamer.AddComment("Loc expr size"); // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB // 1 + ULEB(Rx) + 1 + 1 + 1 return 4 + MCAsmInfo::getULEB128Size(Rx); @@ -203,7 +202,6 @@ unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const { unsigned D1 = 256 + 2 * QReg; unsigned D2 = D1 + 1; - OutStreamer.AddComment("Loc expr size"); // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) + // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8); // 6 + ULEB(D1) + ULEB(D2) @@ -229,10 +227,6 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const { unsigned SReg = Reg - ARM::S0; bool odd = SReg & 0x1; unsigned Rx = 256 + (SReg >> 1); - OutStreamer.AddComment("Loc expr size"); - // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB - // 1 + ULEB(Rx) + 1 + 1 + 1 - EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx)); OutStreamer.AddComment("DW_OP_regx for S register"); EmitInt8(dwarf::DW_OP_regx); @@ -260,12 +254,6 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const { unsigned D1 = 256 + 2 * QReg; unsigned D2 = D1 + 1; - OutStreamer.AddComment("Loc expr size"); - // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) + - // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8); - // 6 + ULEB(D1) + ULEB(D2) - EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2)); - OutStreamer.AddComment("DW_OP_regx for Q register: D1"); EmitInt8(dwarf::DW_OP_regx); EmitULEB128(D1); |
