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path: root/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp
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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-7895/+0
* [ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with...Jiangning Liu2014-05-231-15/+14
* [ARM64] PR19792: Fix cycle in DAG after performPostLD1CombineAdam Nemet2014-05-201-1/+6
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bs...Benjamin Kramer2014-05-191-0/+2
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-171-4/+4
* Target: change member from reference to pointerSaleem Abdulrasool2014-05-171-1/+1
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-161-14/+0
* [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.Hao Liu2014-05-161-1/+94
* Implement global merge optimization for global variables.Jiangning Liu2014-05-151-0/+14
* [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out arg...Jiangning Liu2014-05-151-67/+245
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-4/+4
* Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao2014-05-131-3/+11
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-111-1/+2
* ARM64: fix SELECT_CC lowering in absence of NaNs.Tim Northover2014-05-101-8/+9
* AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM6...Hao Liu2014-05-081-0/+190
* AArch64/ARM64: optimise vector selects & enable testTim Northover2014-05-071-0/+41
* [ARM64-BE] Fix variable-argument saving.James Molloy2014-05-071-1/+2
* [ARM64-BE] Make big endian (scalar) argument passing work correctly.James Molloy2014-05-071-6/+38
* Implememting named register intrinsicsRenato Golin2014-05-061-0/+11
* [ARM64] Enable alignment control option in front-end for ARM64.Kevin Qin2014-05-061-4/+15
* AArch64/ARM64: support indexed loads/stores on vector types.Tim Northover2014-05-021-0/+8
* [ARM64] Prevent bit extraction to be adjusted by following shiftWeiming Zhao2014-04-301-0/+15
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-301-9/+9
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-301-6/+6
* [ARM64] Simplify if condition.James Molloy2014-04-301-6/+2
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introd...Craig Topper2014-04-301-3/+3
* [ARM64]Fix a bug about incorrect operand order in an EXT instruction, which i...Hao Liu2014-04-291-3/+9
* [ARM64]Fix a bug when lowering shuffle vector to an EXT instruction.Hao Liu2014-04-291-28/+23
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-3/+3
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-19/+16
* DAGCombiner: Turn divs of vector splats into vectorized multiplications.Benjamin Kramer2014-04-261-0/+5
* Revert r206749 till a final decision about the intrinsics is made.Michael Zolotukhin2014-04-261-2/+0
* [ARM64] Add RUN lines for "–target arm64 –mattr=-fp-armv8" on AArch64 no-...Kevin Qin2014-04-251-3/+3
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-7/+7
* Add 'musttail' marker to call instructionsReid Kleckner2014-04-241-0/+3
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-231-122/+142
* AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.Tim Northover2014-04-221-11/+20
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
* ARM64: Combine shifts and uses from different basic block to bit-extract inst...Yi Jiang2014-04-211-0/+2
* Reapply r206732. This time without optimization of branches.Michael Zolotukhin2014-04-211-0/+2
* Revert r206732 which is causing llc to crash on most of the build bots.Chandler Carruth2014-04-211-2/+0
* Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN,Michael Zolotukhin2014-04-211-0/+2
* AArch64/ARM64: add non-scalar lowering for more FCVT operations.Tim Northover2014-04-181-2/+8
* AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.Tim Northover2014-04-181-5/+7
* AArch64/ARM64: spot a greater variety of concat_vector operations.Tim Northover2014-04-181-14/+72
* ARM64: spot a vector_shuffle that maps to INS and expand.Tim Northover2014-04-181-0/+64
* AArch64/ARM64: emit all vector FP comparisons as such.Tim Northover2014-04-181-5/+42
* AArch64/ARM64: port BSL logic from AArch64 & enable test.Tim Northover2014-04-181-0/+52
* AArch64/ARM64: copy byval implementation from AArch64.Tim Northover2014-04-181-16/+41
* Improve ARM64 vector creationLouis Gerbarg2014-04-171-2/+2
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