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path: root/llvm/lib/Target/ARM/Thumb2RegisterInfo.h
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* In preparation for moving ARM's TargetRegisterInfo to the TargetMachineEric Christopher2015-03-121-38/+0
| | | | | | | merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable us to match the TargetMachine for our TargetRegisterInfo classes. llvm-svn: 232117
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-121-1/+1
| | | | | | | classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Prune includes in ARM target.Craig Topper2014-03-221-2/+0
| | | | llvm-svn: 204548
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-7/+5
| | | | | | class. llvm-svn: 203433
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-3/+3
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-2/+1
| | | | llvm-svn: 152978
* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-051-1/+2
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. llvm-svn: 127104
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-2/+3
| | | | llvm-svn: 86408
* Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach2009-10-281-2/+0
| | | | | | Thumb2. llvm-svn: 85406
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-13/+0
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-5/+13
| | | | llvm-svn: 77164
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-6/+11
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+1
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-16/+0
| | | | llvm-svn: 75067
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-1/+1
| | | | llvm-svn: 75036
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-9/+8
| | | | llvm-svn: 75020
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-0/+60
Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
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