| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [ARM] Add MVE vector load/store instructions. | Simon Tatham | 2019-06-25 | 1 | -4/+10 |
| * | [ARM] MVE VPT Block Pass | Sjoerd Meijer | 2019-06-14 | 1 | -0/+25 |
| * | [ARM] Fix unused-variable warning in rL363039. | Simon Tatham | 2019-06-11 | 1 | -0/+1 |
| * | [ARM] Add the non-MVE instructions in Arm v8.1-M. | Simon Tatham | 2019-06-11 | 1 | -2/+9 |
| * | Revert rL362953 and its followup rL362955. | Simon Tatham | 2019-06-10 | 1 | -2/+2 |
| * | [ARM] Add the non-MVE instructions in Arm v8.1-M. | Simon Tatham | 2019-06-10 | 1 | -2/+2 |
| * | [ARM] additionally check for ARM::INLINEASM_BR w/ ARM::INLINEASM | Nick Desaulniers | 2019-05-24 | 1 | -1/+1 |
| * | [ARM] Fix FP16 stack loads/stores for Thumb2 with frame pointer | Oliver Stannard | 2019-03-01 | 1 | -2/+2 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [ARM] Enable spilling of the hGPR register class in Thumb2 | Petr Pavlu | 2018-11-08 | 1 | -6/+2 |
| * | ARM: fix Thumb2 CodeGen for ldrex with folded frame-index. | Tim Northover | 2018-09-07 | 1 | -0/+5 |
| * | [DebugInfo] Examine all uses of isDebugValue() for debug instructions. | Shiva Chen | 2018-05-09 | 1 | -2/+2 |
| * | ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR. | Peter Collingbourne | 2018-02-27 | 1 | -1/+2 |
| * | [Thumb] Handle addressing mode AddrMode5FP16 | Sjoerd Meijer | 2018-02-13 | 1 | -0/+14 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -2/+2 |
| * | [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa... | Eugene Zelenko | 2017-06-06 | 1 | -6/+14 |
| * | Re-commit r301040 "X86: Don't emit zero-byte functions on Windows" | Hans Wennborg | 2017-04-21 | 1 | -2/+2 |
| * | Revert r301040 "X86: Don't emit zero-byte functions on Windows" | Hans Wennborg | 2017-04-21 | 1 | -2/+2 |
| * | X86: Don't emit zero-byte functions on Windows | Hans Wennborg | 2017-04-21 | 1 | -2/+2 |
| * | [ARM] Use helpers for adding pred / CC operands. NFC | Diana Picus | 2017-01-20 | 1 | -8/+10 |
| * | [ARM] CodeGen: Remove AddDefaultCC. NFC. | Diana Picus | 2017-01-13 | 1 | -1/+1 |
| * | [ARM] CodeGen: Remove AddDefaultPred. NFC. | Diana Picus | 2017-01-13 | 1 | -20/+31 |
| * | MachineFunction: Return reference for getFrameInfo(); NFC | Matthias Braun | 2016-07-28 | 1 | -2/+2 |
| * | Don't pass Reloc::Model to places that already have it. NFC. | Rafael Espindola | 2016-06-28 | 1 | -6/+6 |
| * | Pass DebugLoc and SDLoc by const ref. | Benjamin Kramer | 2016-06-12 | 1 | -7/+9 |
| * | [Thumb] A branch is not part of an IT block | James Molloy | 2016-06-09 | 1 | -1/+1 |
| * | ARM: Do not attempt to modify register class of physregs. | Matthias Braun | 2016-05-31 | 1 | -4/+9 |
| * | CodeGen: TII: Take MachineInstr& in predicate API, NFC | Duncan P. N. Exon Smith | 2016-02-23 | 1 | -6/+6 |
| * | PseudoSourceValue: Replace global manager with a manager in a machine function. | Alex Lorenz | 2015-08-11 | 1 | -10/+6 |
| * | MC: Modernize MCOperand API naming. NFC. | Jim Grosbach | 2015-05-13 | 1 | -3/+3 |
| * | [ARM] Do not generate invalid encoding for stack adjust, even if this is just | Quentin Colombet | 2015-04-30 | 1 | -2/+7 |
| * | Remove the need to cache the subtarget in the ARM TargetRegisterInfo | Eric Christopher | 2015-03-12 | 1 | -2/+1 |
| * | Fix handling of negative offsets for AddrModeT2_i8s4 in rewriteT2FrameIndex. | Bob Wilson | 2015-02-24 | 1 | -5/+2 |
| * | Fix incorrect immediate size for AddrModeT2_i8s4 in rewriteT2FrameIndex. | Bob Wilson | 2015-02-23 | 1 | -1/+1 |
| * | [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly | Akira Hatanaka | 2014-08-02 | 1 | -3/+3 |
| * | [stack protector] Fix a potential security bug in stack protector where the | Akira Hatanaka | 2014-07-25 | 1 | -0/+9 |
| * | Prune includes in ARM target. | Craig Topper | 2014-03-22 | 1 | -1/+0 |
| * | ARM: remove unnecessary state-tracking during frame lowering. | Tim Northover | 2013-11-04 | 1 | -0/+7 |
| * | Add hint disassembly syntax for 16-bit Thumb hint instructions. | Richard Barton | 2013-10-18 | 1 | -1/+2 |
| * | Fix PR 17372: Emitting PLD for stack address for ARM Thumb2 | Weiming Zhao | 2013-09-26 | 1 | -0/+7 |
| * | Reverting 190043 for now. | Tilmann Scheller | 2013-09-05 | 1 | -14/+2 |
| * | ARM: Add GPR register class excluding LR for use with the ADR instruction. | Tilmann Scheller | 2013-09-05 | 1 | -2/+14 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -1/+1 |
| * | Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. | Michael J. Spencer | 2013-05-24 | 1 | -3/+3 |
| * | ARM: Use ldrd/strd to spill 64-bit pairs when available. | Tim Northover | 2013-04-21 | 1 | -20/+64 |
| * | Remove the explicit MachineInstrBuilder(MI) constructor. | Jakob Stoklund Olesen | 2012-12-19 | 1 | -1/+1 |
| * | Remove all references to TargetInstrInfoImpl. | Jakob Stoklund Olesen | 2012-11-28 | 1 | -2/+2 |
| * | Remove the TII::scheduleTwoAddrSource() hook. | Jakob Stoklund Olesen | 2012-08-13 | 1 | -42/+0 |
| * | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -6/+6 |
| * | Prune some includes | Craig Topper | 2012-03-27 | 1 | -1/+0 |
