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| author | Petr Pavlu <petr.pavlu@arm.com> | 2018-11-08 13:02:10 +0000 |
|---|---|---|
| committer | Petr Pavlu <petr.pavlu@arm.com> | 2018-11-08 13:02:10 +0000 |
| commit | 7c84b2e3abc95eb7b31e0cb7bf06df7c27f9c035 (patch) | |
| tree | fbd7dc43db94bd261a0eef26199829b7ebafa978 /llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | |
| parent | 54c2fa1202cafa98adbb5a8e58c591f3002f54c1 (diff) | |
| download | bcm5719-llvm-7c84b2e3abc95eb7b31e0cb7bf06df7c27f9c035.tar.gz bcm5719-llvm-7c84b2e3abc95eb7b31e0cb7bf06df7c27f9c035.zip | |
[ARM] Enable spilling of the hGPR register class in Thumb2
Generalize code in Thumb2InstrInfo::storeRegToStackSlot() and
loadRegToStackSlot() to allow the GPR class or any of its sub-classes
(including hGPR) to be stored/loaded by ARM::t2STRi12/ARM::t2LDRi12.
Differential Revision: https://reviews.llvm.org/D51927
llvm-svn: 346401
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb2InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index 1a91a703065..d567d333904 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -146,9 +146,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); - if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || - RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || - RC == &ARM::GPRnopcRegClass) { + if (ARM::GPRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(ARM::t2STRi12)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI) @@ -190,9 +188,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); - if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || - RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || - RC == &ARM::GPRnopcRegClass) { + if (ARM::GPRRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) .addFrameIndex(FI) .addImm(0) |
