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path: root/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
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* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-4/+4
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-121-2/+1
| | | | | | | classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-201-1/+1
| | | | | | inquiring for a new one from the TargetMachine. llvm-svn: 229999
* Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequenceJonathan Roelofs2014-08-201-2/+23
| | | | | | | | | | | On pre-v6 hardware, 'MOV lo, lo' gives undefined results, so such copies need to be avoided. This patch trades simplicity for implementation time at the expense of performance... As they say: correctness first, then performance. See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html for a few ideas on how to make this better. llvm-svn: 216138
* [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectlyAkira Hatanaka2014-08-021-3/+3
| | | | | | | | | expanding pseudo LOAD_STATCK_GUARD using instructions that are normally used in pic mode. This patch fixes the bug. <rdar://problem/17886592> llvm-svn: 214614
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-0/+9
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* Prune includes in ARM target.Craig Topper2014-03-221-1/+0
| | | | llvm-svn: 204548
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-1/+1
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-4/+4
| | | | | | since they are equivalent. llvm-svn: 155188
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-1/+0
| | | | llvm-svn: 152978
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-1/+10
| | | | | | | | | | | | | | Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 llvm-svn: 151673
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Make use of MachinePointerInfo::getFixedStack. This removes all mentionJay Foad2011-11-151-5/+2
| | | | | | of PseudoSourceValue from lib/Target/. llvm-svn: 144632
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-11/+1
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-301-2/+2
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-291-2/+2
| | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. llvm-svn: 134092
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+0
| | | | llvm-svn: 134024
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-271-74/+0
| | | | llvm-svn: 120228
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-211-4/+6
| | | | llvm-svn: 114391
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-76/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-111-24/+17
| | | | llvm-svn: 108078
* Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.Bob Wilson2010-06-221-3/+3
| | | | | | Radar 8031193. llvm-svn: 106582
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-3/+3
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-5/+21
| | | | llvm-svn: 104421
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-4/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-8/+10
| | | | llvm-svn: 103193
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-4/+4
| | | | llvm-svn: 100214
* Don't leak a MachineInstruction from ↵Jeffrey Yasskin2010-03-221-0/+2
| | | | | | Thumb1InstrInfo::restoreCalleeSavedRegisters. llvm-svn: 99182
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-2/+0
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
* Update Thumb1 storeRegToStackSlot() and loadRegFromStackSlot() to properlyJim Grosbach2010-01-151-2/+6
| | | | | | | handle physical registers R0-R7 when described as having a non-tGPR register class. llvm-svn: 93564
* Silence a clang warning about the deprecated (but perfectly reasonable inJohn McCall2009-12-161-2/+2
| | | | | | context) increment-of-bool idiom. llvm-svn: 91564
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-19/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Refactor code.Evan Cheng2009-11-081-55/+0
| | | | llvm-svn: 86423
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-1/+1
| | | | llvm-svn: 86408
* t2ldrpci_pic can be used for blockaddress as well.Evan Cheng2009-11-071-3/+14
| | | | llvm-svn: 86400
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-1/+45
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" ↵Anton Korobeynikov2009-11-021-1/+2
| | | | | | stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) llvm-svn: 85764
* Fix a couple more places where we are creating ld / st instructions without ↵Evan Cheng2009-11-011-2/+18
| | | | | | memoperands. llvm-svn: 85746
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-0/+1
| | | | | | | opcode and operand with a tab. Check for these instructions in the usual places. llvm-svn: 85411
* Forgot about ARM::tPUSH. It also has a new writeback operand.Evan Cheng2009-10-021-0/+1
| | | | llvm-svn: 83237
* ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng2009-10-011-0/+1
| | | | llvm-svn: 83214
* It's ok to spill a tGPR register as long as it's still allocated a low register.Evan Cheng2009-08-131-6/+14
| | | | llvm-svn: 78893
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-5/+11
| | | | llvm-svn: 78717
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-2/+1
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-12/+0
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* More DCE.Evan Cheng2009-07-271-4/+0
| | | | llvm-svn: 77231
* Get rid of more dead code.Evan Cheng2009-07-271-2/+0
| | | | llvm-svn: 77227
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-3/+0
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
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