summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2009-10-02 05:03:07 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-10-02 05:03:07 +0000
commitb659dff4eb96a515c5c1f6d14985a599763b03f0 (patch)
tree9148bda39f8e9839d7f5efab620aacb8fe861bd8 /llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
parent2dcee28a61339b6d5b7e5e20f6a4e626f6bc2a5d (diff)
downloadbcm5719-llvm-b659dff4eb96a515c5c1f6d14985a599763b03f0.tar.gz
bcm5719-llvm-b659dff4eb96a515c5c1f6d14985a599763b03f0.zip
Forgot about ARM::tPUSH. It also has a new writeback operand.
llvm-svn: 83237
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb1InstrInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/Thumb1InstrInfo.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index e1f9338bc3f..7eed30edf25 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -156,6 +156,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
AddDefaultPred(MIB);
+ MIB.addReg(0); // No write back.
for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
OpenPOWER on IntegriCloud