| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | ARM cleanup of rot_imm encoding. | Jim Grosbach | 2011-07-26 | 1 | -0/+14 |
| * | ARM assembly parsing and encoding for SSAT16 instruction. | Jim Grosbach | 2011-07-25 | 1 | -2/+2 |
| * | ARM assembly parsing and encoding for SSAT instruction. | Jim Grosbach | 2011-07-25 | 1 | -14/+6 |
| * | Sink ARM mc routines into MCTargetDesc. | Evan Cheng | 2011-07-23 | 1 | -1/+1 |
| * | ARM SSAT instruction 5-bit immediate handling. | Jim Grosbach | 2011-07-22 | 1 | -0/+6 |
| * | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson | 2011-07-21 | 1 | -17/+42 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | ARM PKH shift ammount operand printing tweaks. | Jim Grosbach | 2011-07-20 | 1 | -0/+19 |
| * | Tweak ARM assembly parsing and printing of MSR instruction. | Jim Grosbach | 2011-07-19 | 1 | -2/+15 |
| * | Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple... | Owen Anderson | 2011-07-18 | 1 | -0/+23 |
| * | Flesh out ARM Parser support for shifted-register operands. | Jim Grosbach | 2011-07-13 | 1 | -0/+2 |
| * | Simplify printing of ARM shifted immediates. | Jim Grosbach | 2011-07-11 | 1 | -32/+0 |
| * | Don't hardcode the %reg format in the streamer. | Rafael Espindola | 2011-06-02 | 1 | -2/+2 |
| * | Constants with multiple encodings (ARM): | Johnny Chen | 2011-04-05 | 1 | -2/+3 |
| * | - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT | Bruno Cardoso Lopes | 2011-04-04 | 1 | -5/+45 |
| * | Apply again changes to support ARM memory asm parsing. I removed | Bruno Cardoso Lopes | 2011-03-31 | 1 | -8/+46 |
| * | Revert r128632 again, until I figure out what break the tests | Bruno Cardoso Lopes | 2011-03-31 | 1 | -46/+8 |
| * | Reapply r128585 without generating a lib depedency cycle. An updated log: | Bruno Cardoso Lopes | 2011-03-31 | 1 | -8/+46 |
| * | Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" | Matt Beaumont-Gay | 2011-03-31 | 1 | -49/+8 |
| * | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and | Bruno Cardoso Lopes | 2011-03-30 | 1 | -8/+49 |
| * | Add asm parsing support w/ testcases for strex/ldrex family of instructions | Bruno Cardoso Lopes | 2011-03-24 | 1 | -0/+6 |
| * | Remove some dead patterns. | Jim Grosbach | 2011-03-14 | 1 | -10/+0 |
| * | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 | 1 | -0/+3 |
| * | Add assembly parsing support for "msr" and also fix its encoding. Also add | Bruno Cardoso Lopes | 2011-02-18 | 1 | -1/+8 |
| * | Fix encoding and add parsing support for the arm/thumb CPS instruction: | Bruno Cardoso Lopes | 2011-02-14 | 1 | -20/+12 |
| * | Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ... | Owen Anderson | 2011-02-08 | 1 | -3/+0 |
| * | Add support for printing out floating point values from the ARM assembly | Bill Wendling | 2011-01-26 | 1 | -2/+27 |
| * | Revert 124230. It was causing test failures. | Bill Wendling | 2011-01-25 | 1 | -4/+2 |
| * | The floating point value is encoded in its binary form as an Imm. Convert it | Bill Wendling | 2011-01-25 | 1 | -2/+4 |
| * | Add support to the ARM MC infrastructure to support mcr and friends. This req... | Owen Anderson | 2011-01-13 | 1 | -0/+10 |
| * | The tLDR et al instructions were emitting either a reg/reg or reg/imm | Bill Wendling | 2010-12-14 | 1 | -25/+29 |
| * | Second attempt at converting Thumb2's LDRpci, including updating the gazillio... | Owen Anderson | 2010-12-07 | 1 | -0/+3 |
| * | When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the | Jim Grosbach | 2010-12-03 | 1 | -0/+4 |
| * | Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw | Jim Grosbach | 2010-11-29 | 1 | -8/+0 |
| * | Rename t2 TBB and TBH instructions to reference that they encode the jump table | Jim Grosbach | 2010-11-29 | 1 | -1/+1 |
| * | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 | 1 | -36/+24 |
| * | Minor cleanups: | Bill Wendling | 2010-11-13 | 1 | -6/+8 |
| * | For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled w... | Evan Cheng | 2010-11-12 | 1 | -8/+0 |
| * | The MC code couldn't handle ARM LDR instructions with negative offsets: | Bill Wendling | 2010-11-03 | 1 | -1/+1 |
| * | Remove unused function. | Jim Grosbach | 2010-11-03 | 1 | -8/+0 |
| * | Remove the no longer used 'Modifier' optional operand to the ARM | Jim Grosbach | 2010-11-03 | 1 | -9/+4 |
| * | Remove unused function. | Jim Grosbach | 2010-11-03 | 1 | -10/+0 |
| * | Break ARM addrmode4 (load/store multiple base address) into its constituent | Jim Grosbach | 2010-11-03 | 1 | -13/+4 |
| * | hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes | Chris Lattner | 2010-10-28 | 1 | -0/+6 |
| * | PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. | Jim Grosbach | 2010-10-28 | 1 | -2/+5 |
| * | LDRi12 machine instructions handle negative offset operands normally (simple | Jim Grosbach | 2010-10-27 | 1 | -2/+5 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -0/+5 |
| * | imm12 operands aren't Thumb2 only, so rename the printer helper function. | Jim Grosbach | 2010-10-25 | 1 | -3/+2 |
| * | Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern | Jim Grosbach | 2010-10-13 | 1 | -0/+9 |
| * | Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). | Jim Grosbach | 2010-10-06 | 1 | -4/+2 |
