| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modi... | Johnny Chen | 2011-03-25 | 1 | -0/+5 |
| * | Also need to handle invalid imod values for CPS2p. | Johnny Chen | 2011-03-25 | 1 | -4/+11 |
| * | Handle the added VBICiv*i* NEON instructions, too. | Johnny Chen | 2011-03-24 | 1 | -2/+7 |
| * | The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.c... | Johnny Chen | 2011-03-24 | 1 | -0/+16 |
| * | Add comments to the handling of opcode CPS3p to reject invalid instruction en... | Johnny Chen | 2011-03-24 | 1 | -0/+2 |
| * | CPS3p: Let's reject impossible imod values by returning false from the Disass... | Johnny Chen | 2011-03-24 | 1 | -0/+3 |
| * | Load/Store Multiple: | Johnny Chen | 2011-03-24 | 1 | -4/+4 |
| * | The r128103 fix to cope with the removal of addressing modes from the MC inst... | Johnny Chen | 2011-03-24 | 1 | -2/+7 |
| * | A8.6.399 VSTM: | Johnny Chen | 2011-03-22 | 1 | -12/+2 |
| * | Fixed an assert by the ARM disassembler for LDRD_PRE/POST. | Johnny Chen | 2011-03-19 | 1 | -3/+4 |
| * | There were two issues fixed: | Johnny Chen | 2011-03-15 | 1 | -12/+5 |
| * | Fixed an ARM disassembler bug where it does not handle STRi12 correctly becau... | Johnny Chen | 2011-03-15 | 1 | -6/+9 |
| * | pr9367: Add missing predicated BLX instructions. | Bob Wilson | 2011-03-03 | 1 | -2/+4 |
| * | Add assembly parsing support for "msr" and also fix its encoding. Also add | Bruno Cardoso Lopes | 2011-02-18 | 1 | -7/+11 |
| * | Fix encoding and add parsing support for the arm/thumb CPS instruction: | Bruno Cardoso Lopes | 2011-02-14 | 1 | -9/+19 |
| * | PR9030: Fix disassembly of ARM "mov pc, lr" instruction. | Bob Wilson | 2011-01-28 | 1 | -2/+2 |
| * | s/ARM::BRIND/ARM::BX/g to coincide with r120366. | Bill Wendling | 2010-11-30 | 1 | -3/+3 |
| * | Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw | Jim Grosbach | 2010-11-29 | 1 | -67/+0 |
| * | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 | 1 | -15/+17 |
| * | Break ARM addrmode4 (load/store multiple base address) into its constituent | Jim Grosbach | 2010-11-03 | 1 | -7/+2 |
| * | PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. | Jim Grosbach | 2010-10-28 | 1 | -9/+12 |
| * | Detabify and clean up 80 column violations. | Jim Grosbach | 2010-10-13 | 1 | -2/+2 |
| * | Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern | Jim Grosbach | 2010-10-13 | 1 | -2/+6 |
| * | Fix vmov.f64 disassembly on targets where sizeof(long) != 8. | Benjamin Kramer | 2010-09-17 | 1 | -2/+2 |
| * | store MC FP immediates as a double instead of as an APFloat, thus avoiding an | Jim Grosbach | 2010-09-16 | 1 | -1/+4 |
| * | Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register | Jim Grosbach | 2010-09-15 | 1 | -8/+7 |
| * | Reapply r113875 with additional cleanups. | Jim Grosbach | 2010-09-14 | 1 | -35/+5 |
| * | Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like | Bob Wilson | 2010-08-27 | 1 | -8/+7 |
| * | explicitly handle no-op cases for clarity. Fixes clang warning. | Jim Grosbach | 2010-08-17 | 1 | -0/+3 |
| * | Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid | Bob Wilson | 2010-08-17 | 1 | -6/+20 |
| * | Cleaned up the for-disassembly-only entries in the arm instruction table so that | Johnny Chen | 2010-08-12 | 1 | -2/+9 |
| * | The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td | Johnny Chen | 2010-08-12 | 1 | -0/+2 |
| * | Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. | Johnny Chen | 2010-08-11 | 1 | -3/+0 |
| * | Move the ARM SSAT and USAT optional shift amount operand out of the | Bob Wilson | 2010-08-11 | 1 | -7/+10 |
| * | - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the | Evan Cheng | 2010-08-11 | 1 | -1/+1 |
| * | Add a separate ARM instruction format for Saturate instructions. | Bob Wilson | 2010-08-11 | 1 | -56/+34 |
| * | Add support for disassembling VMVN (immediate) instructions. PR7747. | Bob Wilson | 2010-07-31 | 1 | -0/+4 |
| * | Add a check in the ARM disassembler for NEON instructions that would | Bob Wilson | 2010-07-30 | 1 | -5/+9 |
| * | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 1 | -0/+3 |
| * | Don't assert on an unrecognized BrMiscFrm instruction. | Bob Wilson | 2010-07-29 | 1 | -1/+0 |
| * | Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction | Jim Grosbach | 2010-07-16 | 1 | -3/+5 |
| * | Convert some tab stops into spaces. | Duncan Sands | 2010-07-12 | 1 | -2/+2 |
| * | Renumber NEON instruction formats to be consecutive. | Bob Wilson | 2010-06-26 | 1 | -2/+0 |
| * | Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to | Bob Wilson | 2010-06-25 | 1 | -6/+6 |
| * | Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats. | Bob Wilson | 2010-06-25 | 1 | -16/+3 |
| * | Silence compiler warnings. | Dan Gohman | 2010-06-19 | 1 | -3/+3 |
| * | Start TargetRegisterClass indices at 0 instead of 1, so that | Dan Gohman | 2010-06-18 | 1 | -20/+22 |
| * | Add instruction encoding for the Neon VMOV immediate instruction. This changes | Bob Wilson | 2010-06-11 | 1 | -32/+2 |
| * | Thumb instructions which have reglist operands at the end and predicate operands | Johnny Chen | 2010-04-21 | 1 | -2/+37 |
| * | Better error handling of invalid IT mask '0000', instead of just asserting. | Johnny Chen | 2010-04-19 | 1 | -1/+1 |
