summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
diff options
context:
space:
mode:
authorBill Wendling <isanbard@gmail.com>2010-11-30 00:48:15 +0000
committerBill Wendling <isanbard@gmail.com>2010-11-30 00:48:15 +0000
commit8294a30d547f48e7f6ee9756ad0b2e76d801659c (patch)
tree4e1787f99ec4e19f740e04a866c6d07d5effdf7d /llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
parent90c4947df73cf2251b6ad2c1722547ccc812c66e (diff)
downloadbcm5719-llvm-8294a30d547f48e7f6ee9756ad0b2e76d801659c.tar.gz
bcm5719-llvm-8294a30d547f48e7f6ee9756ad0b2e76d801659c.zip
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
llvm-svn: 120371
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index f73f6faaf94..752e2855dcd 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -790,7 +790,7 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Misc. Branch Instructions.
// BLXr9, BXr9
-// BRIND, BX_RET
+// BX, BX_RET
static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@@ -805,8 +805,8 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
if (Opcode == ARM::BX_RET)
return true;
- // BLXr9 and BRIND take one GPR reg.
- if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
+ // BLXr9 and BX take one GPR reg.
+ if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) {
assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
OpenPOWER on IntegriCloud