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path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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* ARMDisassembler: drop bogus dependency on ARMCodeGenDylan Noblesmith2012-04-031-2/+1
| | | | | | | And indirectly, a dependency on most of the core LLVM optimization libraries. llvm-svn: 153957
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-209/+209
| | | | llvm-svn: 153500
* Added soft fail checks for the disassembler when decoding some corner cases ↵Silviu Baranga2012-03-221-1/+81
| | | | | | of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. llvm-svn: 153252
* Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or ↵Silviu Baranga2012-03-221-3/+31
| | | | | | LDRSHT instruction on ARM llvm-svn: 153251
* Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add testKevin Enderby2012-03-211-0/+19
| | | | | | case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp . llvm-svn: 153218
* The ARM instructions that have an unpredictable behavior when the pc ↵Silviu Baranga2012-03-201-2/+8
| | | | | | register operand is given now fail with soft fail. Modified the regression tests to reflect this. llvm-svn: 153089
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-6/+6
| | | | | | specific backends. llvm-svn: 152537
* Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach2012-03-071-6/+0
| | | | llvm-svn: 152184
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-0/+7
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-25/+41
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby2012-03-061-7/+7
| | | | llvm-svn: 152127
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-0/+50
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-6/+89
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MemoryObject accessor members const againDerek Schuff2012-02-291-4/+4
| | | | llvm-svn: 151687
* Fix the symbolic operand added for the C disassmbler API for the ARM blKevin Enderby2012-02-271-1/+1
| | | | | | thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode. llvm-svn: 151530
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-231-33/+35
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Make the EDis tables const.Benjamin Kramer2012-02-111-4/+4
| | | | llvm-svn: 150304
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-1/+1
| | | | llvm-svn: 149961
* Enable streaming of bitcodeDerek Schuff2012-02-061-4/+4
| | | | | | | This CL delays reading of function bodies from initial parse until materialization, allowing overlap of compilation with bitcode download. llvm-svn: 149918
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+1
| | | | llvm-svn: 148578
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-151-4/+1
| | | | llvm-svn: 146691
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-141-9/+18
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-30/+0
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-9/+18
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* Remove unused variableMatt Beaumont-Gay2011-11-301-2/+0
| | | | llvm-svn: 145517
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-301-10/+6
| | | | llvm-svn: 145510
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-28/+8
| | | | llvm-svn: 145450
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-291-20/+8
| | | | llvm-svn: 145442
* Fix a misplaced paren bug.Owen Anderson2011-11-151-1/+1
| | | | llvm-svn: 144692
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and ↵Owen Anderson2011-11-151-8/+62
| | | | | | VMOVv4f32. llvm-svn: 144683
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-121-4/+0
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
| | | | llvm-svn: 144384
* The rules disallowing single-register reglist operands only apply to the POP ↵Owen Anderson2011-11-021-5/+1
| | | | | | alias, not to LDM/STM instructions. Revert r143552. llvm-svn: 143553
* Register list operands are not allowed to contain only a single register. ↵Owen Anderson2011-11-021-1/+5
| | | | | | Alternate encodings are used in that case. llvm-svn: 143552
* Fix disassembly of some VST1 instructions.Owen Anderson2011-11-011-5/+19
| | | | llvm-svn: 143507
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-12/+16
| | | | llvm-svn: 143369
* More not-crashing NEON disassembly updates for the vld refactoring.Owen Anderson2011-10-311-0/+4
| | | | llvm-svn: 143351
* Reapply r143202, with a manual decoding hook for SWP. This change ↵Owen Anderson2011-10-281-0/+24
| | | | | | inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. llvm-svn: 143208
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson2011-10-271-0/+4
| | | | | | previously. llvm-svn: 143162
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-4/+8
| | | | | | Four entry register lists. llvm-svn: 142882
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-4/+8
| | | | | | Three entry register list variation. llvm-svn: 142876
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-12/+51
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson2011-10-241-6/+0
| | | | | | more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. llvm-svn: 142817
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-1/+1
| | | | | | correctness along the way. llvm-svn: 142726
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-211-18/+0
| | | | llvm-svn: 142704
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+0
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-24/+0
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-16/+0
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-8/+0
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
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