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authorJim Grosbach <grosbach@apple.com>2011-11-12 00:31:53 +0000
committerJim Grosbach <grosbach@apple.com>2011-11-12 00:31:53 +0000
commit8ca13deecfc7cb08486c4a44cfe3d74b82fceab6 (patch)
treea15e1d5173141cbc87c65de0ffee2096e252dc05 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent0daa607f5580332542711a4343dbb0298811418c (diff)
downloadbcm5719-llvm-8ca13deecfc7cb08486c4a44cfe3d74b82fceab6.tar.gz
bcm5719-llvm-8ca13deecfc7cb08486c4a44cfe3d74b82fceab6.zip
Re-apply 144430, this time with the associated isel and disassmbler bits.
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp4
1 files changed, 0 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 840f50bdf55..0b9b5d0e6d2 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2267,10 +2267,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second input register
switch (Inst.getOpcode()) {
- case ARM::VST1q8:
- case ARM::VST1q16:
- case ARM::VST1q32:
- case ARM::VST1q64:
case ARM::VST1d8T:
case ARM::VST1d16T:
case ARM::VST1d32T:
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