| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Tidy up. Trailing whitespace. | Jim Grosbach | 2011-10-20 | 1 | -2/+2 |
| * | Removed set, but unused variables. | Chad Rosier | 2011-10-17 | 1 | -10/+0 |
| * | Fix a non-firing assert. Change: | Richard Trieu | 2011-10-14 | 1 | -1/+1 |
| * | Fix undefined shift. Patch by Ahmed Charles. | Eli Friedman | 2011-10-13 | 1 | -1/+1 |
| * | SETEND is not allowed in an IT block. | Owen Anderson | 2011-10-13 | 1 | -0/+1 |
| * | ARM addrmode5 represents the 'U' bit of the encoding backwards. | Jim Grosbach | 2011-10-12 | 1 | -14/+17 |
| * | Thumb2 assembly parsing and encoding for LDC/STC. | Jim Grosbach | 2011-10-12 | 1 | -24/+50 |
| * | addrmode2 is gone from these, so no need for the reg0 operand. | Jim Grosbach | 2011-10-12 | 1 | -24/+0 |
| * | Fix the check for nested IT instructions in the disassembler. We need to per... | Owen Anderson | 2011-10-06 | 1 | -3/+6 |
| * | Adding back support for printing operands symbolically to ARM's new disassembler | Kevin Enderby | 2011-10-04 | 1 | -3/+211 |
| * | ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. | Jim Grosbach | 2011-09-30 | 1 | -27/+0 |
| * | ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. | Owen Anderson | 2011-09-26 | 1 | -0/+14 |
| * | Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t... | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | Revert r140412. This affects more instructions than intended. | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | Thumb2 register-shifted-register loads cannot target the PC or the SP. | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | tMOVSr is not allowed in an IT block either. | Owen Anderson | 2011-09-19 | 1 | -0/+1 |
| * | CPS instructions are UNPREDICTABLE inside IT blocks. | Owen Anderson | 2011-09-19 | 1 | -0/+4 |
| * | Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not... | Owen Anderson | 2011-09-19 | 1 | -0/+2 |
| * | Thumb2 assembly parsing and encoding for TBB/TBH. | Jim Grosbach | 2011-09-19 | 1 | -0/+18 |
| * | Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por... | Owen Anderson | 2011-09-19 | 1 | -0/+3 |
| * | Bitfield mask instructions are unpredictable if the encoded LSB is higher tha... | Owen Anderson | 2011-09-16 | 1 | -1/+4 |
| * | Fix bitfield decoding based on Eli's feedback. | Owen Anderson | 2011-09-16 | 1 | -4/+3 |
| * | Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. | Owen Anderson | 2011-09-16 | 1 | -1/+1 |
| * | Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). | Owen Anderson | 2011-09-16 | 1 | -0/+4 |
| * | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson | 2011-09-16 | 1 | -1/+4 |
| * | Don't attach annotations to MCInst's. Instead, have the disassembler return,... | Owen Anderson | 2011-09-15 | 1 | -4/+8 |
| * | Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. | Owen Anderson | 2011-09-14 | 1 | -0/+4 |
| * | Port more encoding tests to decoding tests, and correct an improper Thumb2 pr... | Owen Anderson | 2011-09-12 | 1 | -0/+32 |
| * | LDM writeback is not allowed if Rn is in the target register list. | Owen Anderson | 2011-09-09 | 1 | -0/+19 |
| * | Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. | Owen Anderson | 2011-09-09 | 1 | -0/+18 |
| * | Thumb unconditional branches are allowed in IT blocks, and therefore should h... | Owen Anderson | 2011-09-09 | 1 | -4/+14 |
| * | Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. | Jim Grosbach | 2011-09-09 | 1 | -0/+17 |
| * | All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. | Owen Anderson | 2011-09-08 | 1 | -2/+3 |
| * | Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. | Owen Anderson | 2011-09-08 | 1 | -12/+21 |
| * | Thumb2 assembly parsing and encoding for LDRD(immediate). | Jim Grosbach | 2011-09-08 | 1 | -0/+76 |
| * | Remove the "common" set of instructions shared between ARM and Thumb2 modes. ... | Owen Anderson | 2011-09-08 | 1 | -18/+0 |
| * | Create Thumb2 versions of STC/LDC, and reenable the relevant tests. | Owen Anderson | 2011-09-07 | 1 | -0/+28 |
| * | Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds p... | James Molloy | 2011-09-07 | 1 | -16/+23 |
| * | Port more assembler tests over to disassembler tests, and fix a minor logic e... | Owen Anderson | 2011-09-07 | 1 | -1/+1 |
| * | Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ... | James Molloy | 2011-09-07 | 1 | -8/+9 |
| * | Merge the ARM disassembler header into the implementation file, since it is n... | Owen Anderson | 2011-09-01 | 1 | -1/+54 |
| * | Fix 80 columns violations. | Owen Anderson | 2011-09-01 | 1 | -449/+655 |
| * | Fix up r137380 based on post-commit review by Jim Grosbach. | James Molloy | 2011-09-01 | 1 | -593/+595 |
| * | The asm parser currently selects the wrong encoding for non-conditional Thumb... | Owen Anderson | 2011-08-31 | 1 | -4/+4 |
| * | Fix issues with disassembly of IT instructions involving condition codes othe... | Owen Anderson | 2011-08-30 | 1 | -28/+30 |
| * | Improve encoding support for BLX with immediat eoperands, and fix a BLX decod... | Owen Anderson | 2011-08-26 | 1 | -9/+0 |
| * | Spelling fail. | Owen Anderson | 2011-08-26 | 1 | -1/+1 |
| * | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson | 2011-08-26 | 1 | -2/+49 |
| * | Update for feedback from Jim. | Owen Anderson | 2011-08-26 | 1 | -3/+3 |
| * | ARMDisassembler: Always return a size, even when disassembling fails. | Benjamin Kramer | 2011-08-26 | 1 | -3/+11 |
