| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not... | Owen Anderson | 2011-09-19 | 1 | -0/+2 |
| * | Thumb2 assembly parsing and encoding for TBB/TBH. | Jim Grosbach | 2011-09-19 | 1 | -0/+18 |
| * | Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por... | Owen Anderson | 2011-09-19 | 1 | -0/+3 |
| * | Bitfield mask instructions are unpredictable if the encoded LSB is higher tha... | Owen Anderson | 2011-09-16 | 1 | -1/+4 |
| * | Fix bitfield decoding based on Eli's feedback. | Owen Anderson | 2011-09-16 | 1 | -4/+3 |
| * | Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. | Owen Anderson | 2011-09-16 | 1 | -1/+1 |
| * | Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). | Owen Anderson | 2011-09-16 | 1 | -0/+4 |
| * | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson | 2011-09-16 | 1 | -1/+4 |
| * | Don't attach annotations to MCInst's. Instead, have the disassembler return,... | Owen Anderson | 2011-09-15 | 1 | -4/+8 |
| * | Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. | Owen Anderson | 2011-09-14 | 1 | -0/+4 |
| * | Port more encoding tests to decoding tests, and correct an improper Thumb2 pr... | Owen Anderson | 2011-09-12 | 1 | -0/+32 |
| * | LDM writeback is not allowed if Rn is in the target register list. | Owen Anderson | 2011-09-09 | 1 | -0/+19 |
| * | Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. | Owen Anderson | 2011-09-09 | 1 | -0/+18 |
| * | Thumb unconditional branches are allowed in IT blocks, and therefore should h... | Owen Anderson | 2011-09-09 | 1 | -4/+14 |
| * | Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. | Jim Grosbach | 2011-09-09 | 1 | -0/+17 |
| * | All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. | Owen Anderson | 2011-09-08 | 1 | -2/+3 |
| * | Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. | Owen Anderson | 2011-09-08 | 1 | -12/+21 |
| * | Thumb2 assembly parsing and encoding for LDRD(immediate). | Jim Grosbach | 2011-09-08 | 1 | -0/+76 |
| * | Remove the "common" set of instructions shared between ARM and Thumb2 modes. ... | Owen Anderson | 2011-09-08 | 1 | -18/+0 |
| * | Create Thumb2 versions of STC/LDC, and reenable the relevant tests. | Owen Anderson | 2011-09-07 | 1 | -0/+28 |
| * | Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds p... | James Molloy | 2011-09-07 | 1 | -16/+23 |
| * | Port more assembler tests over to disassembler tests, and fix a minor logic e... | Owen Anderson | 2011-09-07 | 1 | -1/+1 |
| * | Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ... | James Molloy | 2011-09-07 | 1 | -8/+9 |
| * | Merge the ARM disassembler header into the implementation file, since it is n... | Owen Anderson | 2011-09-01 | 1 | -1/+54 |
| * | Fix 80 columns violations. | Owen Anderson | 2011-09-01 | 1 | -449/+655 |
| * | Fix up r137380 based on post-commit review by Jim Grosbach. | James Molloy | 2011-09-01 | 1 | -593/+595 |
| * | The asm parser currently selects the wrong encoding for non-conditional Thumb... | Owen Anderson | 2011-08-31 | 1 | -4/+4 |
| * | Fix issues with disassembly of IT instructions involving condition codes othe... | Owen Anderson | 2011-08-30 | 1 | -28/+30 |
| * | Improve encoding support for BLX with immediat eoperands, and fix a BLX decod... | Owen Anderson | 2011-08-26 | 1 | -9/+0 |
| * | Spelling fail. | Owen Anderson | 2011-08-26 | 1 | -1/+1 |
| * | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson | 2011-08-26 | 1 | -2/+49 |
| * | Update for feedback from Jim. | Owen Anderson | 2011-08-26 | 1 | -3/+3 |
| * | ARMDisassembler: Always return a size, even when disassembling fails. | Benjamin Kramer | 2011-08-26 | 1 | -3/+11 |
| * | Support an extension of ARM asm syntax to allow immediate operands to ADR ins... | Owen Anderson | 2011-08-26 | 1 | -6/+9 |
| * | Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT i... | Owen Anderson | 2011-08-26 | 1 | -0/+2 |
| * | Port over additional encoding tests to decoding tests, and fix an operand ord... | Owen Anderson | 2011-08-25 | 1 | -1/+1 |
| * | Perform more thorough checking of t2IT mask parameters, which fixes all remai... | Owen Anderson | 2011-08-24 | 1 | -0/+13 |
| * | Be careful not to walk off the end of the operand info list while updating VF... | Owen Anderson | 2011-08-24 | 1 | -1/+2 |
| * | Move TargetRegistry and TargetSelect from Target to Support where they belong. | Evan Cheng | 2011-08-24 | 1 | -1/+1 |
| * | Be stricter in enforcing IT instruction predicate values, so that we don't en... | Owen Anderson | 2011-08-24 | 1 | -0/+14 |
| * | Fix decoding of Thumb2 prefetch instructions, which account for all the remai... | Owen Anderson | 2011-08-23 | 1 | -3/+9 |
| * | Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same in... | Owen Anderson | 2011-08-23 | 1 | -9/+43 |
| * | Reject invalid imod values in t2CPS instructions. | Owen Anderson | 2011-08-22 | 1 | -1/+10 |
| * | Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming major... | Owen Anderson | 2011-08-22 | 1 | -0/+45 |
| * | Fix another batch of VLD/VST decoding crashes discovered by randomized testing. | Owen Anderson | 2011-08-22 | 1 | -16/+40 |
| * | Correct writeback handling of duplicating VLD instructions. Discovered by ra... | Owen Anderson | 2011-08-22 | 1 | -4/+4 |
| * | Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ... | Owen Anderson | 2011-08-22 | 1 | -1/+1 |
| * | STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST fo... | Owen Anderson | 2011-08-18 | 1 | -0/+4 |
| * | Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ... | Owen Anderson | 2011-08-18 | 1 | -8/+42 |
| * | Remember to fill in some operands so we can print _something_ coherent even w... | Owen Anderson | 2011-08-18 | 1 | -1/+4 |
