summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach2010-10-011-733/+0
| | | | | | | been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. llvm-svn: 115360
* Now that the pseudos that needed this are all custom lowered, we can go backJim Grosbach2010-09-301-8/+0
| | | | | | to an empty PrintSpecial() llvm-svn: 115128
* Nuke it from orbit. It's the only way to be sure.Jim Grosbach2010-09-301-5/+0
| | | | | | (Kill the dead non-MC asm printer for the ARM target.) llvm-svn: 115127
* Add PrintSpecial() handling for in ARM MC instruction printer.Jim Grosbach2010-09-221-0/+8
| | | | llvm-svn: 114563
* PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach2010-09-181-3/+2
| | | | | | with one in the generic printing code is an error. llvm-svn: 114242
* Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach2010-09-171-0/+1
| | | | | | and shift instructions on ARM. Update the tests to match. llvm-svn: 114230
* Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach2010-09-171-5/+4
| | | | llvm-svn: 114215
* MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach2010-09-161-1/+4
| | | | | | (PICLDRB, et. al.) and PICSTR* llvm-svn: 114098
* Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson2010-09-161-29/+1
| | | | | | used for anything. llvm-svn: 114067
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-161-2/+2
| | | | | | unnecessary dtor for MCOperand. llvm-svn: 114064
* Add support for the 'lane' modifier on vdup operandsJim Grosbach2010-09-151-7/+25
| | | | llvm-svn: 114030
* Reduce dependencies in the ARM MC instruction printer.Jim Grosbach2010-09-151-1/+1
| | | | llvm-svn: 114009
* Add support for floating point immediates to MC instruction printing. ARMJim Grosbach2010-09-151-2/+2
| | | | | | | | | | | VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... llvm-svn: 113996
* Reapply r113875 with additional cleanups.Jim Grosbach2010-09-141-77/+23
| | | | | | | | | | | | | | | "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. llvm-svn: 113903
* revert 113875 momentarilly. Need to fix the MC disassembler to handle theJim Grosbach2010-09-141-23/+77
| | | | | | change. llvm-svn: 113878
* trailing whitespace cleanupJim Grosbach2010-09-141-23/+23
| | | | llvm-svn: 113877
* The register specified for a dregpair is the corresponding Q register, so toJim Grosbach2010-09-141-77/+23
| | | | | | | | get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01]). llvm-svn: 113875
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-12/+2
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson2010-08-161-2/+2
| | | | | | instructions besides saturate instructions. No functional changes. llvm-svn: 111168
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-0/+6
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-3/+22
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* ARM "rrx" shift operands do not have an immediate. PR7790.Bob Wilson2010-08-051-12/+9
| | | | llvm-svn: 110292
* Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson2010-07-141-1/+1
| | | | | | | instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. llvm-svn: 108386
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-131-29/+3
| | | | | | avoid replicated code. llvm-svn: 108227
* Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson2010-07-021-2/+2
| | | | | | | that it checks the immediate values, not just the instructions opcodes. Radar 8110263. llvm-svn: 107487
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-18/+32
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-2/+2
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Add support for movi32 of global values to the new (MC) asm printer.Rafael Espindola2010-05-121-1/+2
| | | | llvm-svn: 103576
* Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen2010-04-161-0/+20
| | | | | | | | | | case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). llvm-svn: 101557
* In the same spirit of r101524, which removed the assert() from ↵Johnny Chen2010-04-161-1/+0
| | | | | | | | printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. llvm-svn: 101529
* Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" areJohnny Chen2010-04-161-1/+0
| | | | | | | | | considered legal instructions. Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM) -- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395. llvm-svn: 101524
* Replace r101053 with a fix for getSOImmValRotate() so that it will correctlyBob Wilson2010-04-131-1/+1
| | | | | | | recognize all the valid rotated immediates. This fixes the disassembler issue and will also help codegen for some unusual constant values. llvm-svn: 101114
* Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after callingJohnny Chen2010-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2. Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V). [12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done (gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble (gdb) r Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble Reading symbols for shared libraries ++. done 0xf5 0x71 0xf0 0x53 Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1| ------------------------------------------------------------------------------------------------- mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229. Program received signal SIGABRT, Aborted. 0x00007fff88c65886 in __kill () (gdb) bt #0 0x00007fff88c65886 in __kill () #1 0x00007fff88d05eae in abort () #2 0x00007fff88cf2ef0 in __assert_rtn () #3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229 #4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254 #5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236 #6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182 #7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65 #8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153 #9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347 #10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374 (gdb) q The program is running. Exit anyway? (y or n) y [13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ llvm-svn: 101053
* fix an ugly wart in the MCInstPrinter api where theChris Lattner2010-04-041-1/+1
| | | | | | | | raw_ostream to print an instruction to had to be specified at MCInstPrinter construction time instead of being able to pick at each call to printInstruction. llvm-svn: 100307
* change a ton of code to not implicitly use the "O" raw_ostreamChris Lattner2010-04-041-59/+96
| | | | | | member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-9/+14
| | | | | | | with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
* Fix -Asserts warnings.Daniel Dunbar2010-03-191-5/+4
| | | | llvm-svn: 98928
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-171-18/+409
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-161-5/+9
| | | | llvm-svn: 98692
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-161-9/+5
| | | | | | | optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. llvm-svn: 98683
* Remove redundant writeback flag in ARM addressing mode 5.Bob Wilson2010-03-161-2/+0
| | | | llvm-svn: 98648
* Remove the writeback flag from ARM's address mode 4. Now that we have separateBob Wilson2010-03-161-2/+0
| | | | | | instructions for ld/st with writeback, the flag is completely redundant. llvm-svn: 98643
* Fix unused variable warnings.Bob Wilson2010-03-161-1/+0
| | | | llvm-svn: 98642
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-415/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-18/+415
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson2010-03-161-9/+1
| | | | | | | This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. llvm-svn: 98635
* AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen2010-03-021-0/+6
| | | | | | | Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution llvm-svn: 97571
* sink handling of target-independent machine instrs (otherChris Lattner2010-02-031-1/+0
| | | | | | | | than DEBUG_VALUE :( ) into the target indep AsmPrinter.cpp file. This allows elimination of the NO_ASM_WRITER_BOILERPLATE hack among other things. llvm-svn: 95177
* Implemented ARMInstPrinter::printThumbS4ImmOperand().Johnny Chen2010-01-251-2/+1
| | | | llvm-svn: 94457
* remove the MAI argument to MCExpr::print and switch overthing to use << when ↵Chris Lattner2010-01-181-1/+1
| | | | | | printing them. llvm-svn: 93699
OpenPOWER on IntegriCloud