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* Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach2010-10-014-871/+0
| | | | | | | been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. llvm-svn: 115360
* Now that the pseudos that needed this are all custom lowered, we can go backJim Grosbach2010-09-302-9/+1
| | | | | | to an empty PrintSpecial() llvm-svn: 115128
* Nuke it from orbit. It's the only way to be sure.Jim Grosbach2010-09-301-5/+0
| | | | | | (Kill the dead non-MC asm printer for the ARM target.) llvm-svn: 115127
* nuke unused varJim Grosbach2010-09-231-1/+0
| | | | llvm-svn: 114676
* Add PrintSpecial() handling for in ARM MC instruction printer.Jim Grosbach2010-09-222-2/+9
| | | | llvm-svn: 114563
* Add start of support for MC instruction printer of ARM jump tables. Filling inJim Grosbach2010-09-211-0/+2
| | | | | | the rest of it is next up. llvm-svn: 114500
* PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach2010-09-181-3/+2
| | | | | | with one in the generic printing code is an error. llvm-svn: 114242
* Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach2010-09-171-0/+1
| | | | | | and shift instructions on ARM. Update the tests to match. llvm-svn: 114230
* Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach2010-09-172-7/+5
| | | | llvm-svn: 114215
* trailing whitespaceJim Grosbach2010-09-171-8/+8
| | | | llvm-svn: 114212
* MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach2010-09-161-1/+4
| | | | | | (PICLDRB, et. al.) and PICSTR* llvm-svn: 114098
* Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson2010-09-161-29/+1
| | | | | | used for anything. llvm-svn: 114067
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-161-2/+2
| | | | | | unnecessary dtor for MCOperand. llvm-svn: 114064
* Add support for the 'lane' modifier on vdup operandsJim Grosbach2010-09-151-7/+25
| | | | llvm-svn: 114030
* Reduce dependencies in the ARM MC instruction printer.Jim Grosbach2010-09-151-1/+1
| | | | llvm-svn: 114009
* Add support for floating point immediates to MC instruction printing. ARMJim Grosbach2010-09-151-2/+2
| | | | | | | | | | | VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... llvm-svn: 113996
* Reapply r113875 with additional cleanups.Jim Grosbach2010-09-141-77/+23
| | | | | | | | | | | | | | | "The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. llvm-svn: 113903
* revert 113875 momentarilly. Need to fix the MC disassembler to handle theJim Grosbach2010-09-141-23/+77
| | | | | | change. llvm-svn: 113878
* trailing whitespace cleanupJim Grosbach2010-09-141-23/+23
| | | | llvm-svn: 113877
* The register specified for a dregpair is the corresponding Q register, so toJim Grosbach2010-09-141-77/+23
| | | | | | | | get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01]). llvm-svn: 113875
* Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."Michael J. Spencer2010-09-131-2/+0
| | | | | | | | | | This reverts commit r113632 Conflicts: cmake/modules/AddLLVM.cmake llvm-svn: 113819
* CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.Michael J. Spencer2010-09-101-0/+2
| | | | llvm-svn: 113632
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-12/+2
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson2010-08-162-3/+3
| | | | | | instructions besides saturate instructions. No functional changes. llvm-svn: 111168
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-122-0/+7
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-112-3/+23
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* ARM "rrx" shift operands do not have an immediate. PR7790.Bob Wilson2010-08-051-12/+9
| | | | llvm-svn: 110292
* Update CMake files.Daniel Dunbar2010-07-201-2/+0
| | | | llvm-svn: 108787
* sink the arm implementations of ASmPrinter and MCInstLowerChris Lattner2010-07-193-1656/+0
| | | | | | | | out of the AsmPrinter directory into libarm. Now the ARM InstPrinters depend jsut on the MC stuff, not on vmcore or codegen. llvm-svn: 108783
* Split -enable-finite-only-fp-math to two options:Evan Cheng2010-07-151-1/+1
| | | | | | -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. llvm-svn: 108465
* Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson2010-07-142-6/+2
| | | | | | | instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. llvm-svn: 108386
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-132-58/+6
| | | | | | avoid replicated code. llvm-svn: 108227
* Convert some tab stops into spaces.Duncan Sands2010-07-121-4/+4
| | | | llvm-svn: 108130
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-1/+1
| | | | | | consistency with other instructions that have lists of register operands. llvm-svn: 107944
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-061-1/+5
| | | | llvm-svn: 107701
* Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson2010-07-022-4/+4
| | | | | | | that it checks the immediate values, not just the instructions opcodes. Radar 8110263. llvm-svn: 107487
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-113-39/+69
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Use report_fatal_error, not llvm_unreachable.Evan Cheng2010-05-271-1/+1
| | | | llvm-svn: 104899
* llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng2010-05-271-18/+2
| | | | llvm-svn: 104891
* Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' casesBob Wilson2010-05-271-11/+17
| | | | | | | should fall through to the 'H' case, but instead 'Q' was falling through to 'R' so that it would do the wrong thing for a big-endian ARM target. llvm-svn: 104883
* Use enums instead of literals in the ARM backend.Jakob Stoklund Olesen2010-05-251-2/+2
| | | | llvm-svn: 104573
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-242-4/+4
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Add support for movi32 of global values to the new (MC) asm printer.Rafael Espindola2010-05-122-5/+25
| | | | llvm-svn: 103576
* I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename itDuncan Sands2010-05-111-1/+1
| | | | | | | to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is the opposite, for future use by dragonegg. llvm-svn: 103495
* Handle target-specific form of DBG_VALUE in AsmPrinter.Dale Johannesen2010-04-261-0/+19
| | | | llvm-svn: 102373
* Add const qualifiers to TargetLoweringObjectFile usage.Dan Gohman2010-04-171-4/+5
| | | | llvm-svn: 101640
* Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen2010-04-162-4/+24
| | | | | | | | | | case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). llvm-svn: 101557
* In the same spirit of r101524, which removed the assert() from ↵Johnny Chen2010-04-162-2/+0
| | | | | | | | printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. llvm-svn: 101529
* Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" areJohnny Chen2010-04-162-2/+0
| | | | | | | | | considered legal instructions. Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM) -- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395. llvm-svn: 101524
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-2/+2
| | | | llvm-svn: 101334
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