summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Commit message (Expand)AuthorAgeFilesLines
* [ARM] Set up infrastructure for MVE vector instructions.Simon Tatham2019-06-131-65/+424
* [ARM] Refactor handling of IT mask operands.Simon Tatham2019-06-131-46/+37
* [ARM] First MVE instructions: scalar shifts.Mikhail Maltsev2019-06-111-0/+9
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-24/+273
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-111-1/+1
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-101-1/+1
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-101-273/+24
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-24/+273
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-15/+16
* [ARM] Create a TargetInfo header. NFCRichard Trieu2019-05-141-0/+1
* [ARM] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-111-1/+1
* ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover2019-04-231-0/+14
* Test commit accessOliver Stannard2019-04-111-0/+1
* [ARM][Asm] Accept upper case coprocessor number and registersOliver Stannard2019-03-261-2/+2
* Add XCOFF triple object format type for AIXJason Liu2019-03-121-0/+3
* Use bitset for assembler predicatesStanislav Mekhanoshin2019-03-111-53/+55
* [ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham2019-02-251-0/+12
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM][MC] Move information about variadic register defs into tablegenOliver Stannard2018-12-031-25/+1
* [ARM][Asm] Debug trace for the processInstruction loopOliver Stannard2018-12-031-1/+7
* [ARM][AsmParser] Improve debug printing of parsed asm operandsOliver Stannard2018-11-231-19/+39
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-281-1/+22
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-271-1/+2
* [Arm][AsmParser] Restrict register list size for VSTM/VLDMLuke Cheeseman2018-09-241-0/+9
* Fix for bug 34002 - label generated before it block is finalized. Differentia...Maya Madhavan2018-09-201-1/+6
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-171-2/+4
* [ARM] Allow automatically deducing the thumb instruction size for .instMartin Storsjo2018-07-311-3/+14
* [ARM] Support the .inst directive for MachO and COFF targetsMartin Storsjo2018-07-311-6/+6
* Remove trailing spaceFangrui Song2018-07-301-11/+11
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-061-0/+49
* [ARM] [Assembler] Support negative immediates: cover few missing casesVolodymyr Turanskyy2018-07-041-2/+7
* [ARM] Add missing Thumb2 assembler diagnostics.Eli Friedman2018-06-281-62/+116
* ARM: diagnose unpredictable IT instructionsTim Northover2018-06-261-0/+15
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-4/+5
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-3/+3
* [ARM] Do not convert some vmov instructionsMikhail Maltsev2018-04-041-8/+6
* [ARM] Fix warnings about missing parentheses in ARMAsmParserMikhail Maltsev2018-03-191-3/+6
* [ARM] Convert more invalid NEON immediate loadsMikhail Maltsev2018-03-161-43/+102
* [ARM] Fix a check in vmov/vmvn immediate parsingMikhail Maltsev2018-03-161-20/+13
* [ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath2018-03-061-0/+12
* [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registersOliver Stannard2018-03-051-0/+18
* [ARM] Don't print "Requires NEON" error message for M-profileAndre Vieira2018-02-131-0/+2
* [ARM][AArch64] Add CSDB speculation barrier instructionOliver Stannard2018-02-061-11/+14
* Fix -Wsign-compare warnings on WindowsReid Kleckner2018-01-051-4/+5
* [ARM] Issue an erorr when non-general-purpose registers are used in address o...Momchil Velikov2018-01-051-8/+31
* [ARM] Armv8-R DFB instructionSam Parker2017-12-211-5/+5
* Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard2017-12-041-17/+0
* [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard2017-12-041-0/+17
* [ARM] Remove pre-UAL FLDM/FSTM aliasesOliver Stannard2017-11-211-36/+0
* [ARM] Don't omit non-default predication codeOliver Stannard2017-11-211-3/+4
OpenPOWER on IntegriCloud