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path: root/llvm/lib/Target/ARM/AsmParser
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* CMake: Make most target symbols hidden by defaultTom Stellard2020-01-141-1/+1
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-21/+72
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-71/+21
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-21/+71
* [NFC] Fix trivial typos in commentsJames Henderson2020-01-061-1/+1
* [ARM][MVE][Intrinsics] Add VMULL[BT]Q_(INT|POLY) intrinsics.Mark Murray2019-12-091-4/+4
* [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"Tom Stellard2019-11-211-1/+1
* [ARM][AsmParser] handles offset expression in parenthesesJian Cai2019-10-141-5/+7
* Fix uninitialized variable warning. NFCISimon Pilgrim2019-10-031-1/+1
* Cosmetic; don't use the magic constant 35 when HASH is more readable. This ma...Mark Murray2019-09-231-3/+3
* [ARM] VFPv2 only supports 16 D registers.Eli Friedman2019-09-171-2/+2
* [ARM][AsmParser] Don't dereference a dyn_cast result. NFCI.Simon Pilgrim2019-09-171-50/+41
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-30/+30
* [ARM] Fix detection of duplicates when parsing reg list operandsMomchil Velikov2019-08-131-19/+43
* [ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev2019-07-191-0/+16
* [ARM] Relax constraints on operands of VQxDMLxDH instructionsMikhail Maltsev2019-07-081-9/+1
* [ARM] Make coprocessor number restrictions consistent.Simon Tatham2019-06-271-2/+2
* [ARM] Add remaining miscellaneous MVE instructions.Simon Tatham2019-06-251-19/+18
* [ARM] Add MVE vector load/store instructions.Simon Tatham2019-06-251-38/+253
* [ARM] Add MVE interleaving load/store family.Simon Tatham2019-06-241-22/+83
* [ARM] Add MVE 64-bit GPR <-> vector move instructions.Simon Tatham2019-06-211-0/+44
* [ARM] Add MVE vector instructions that take a scalar input.Simon Tatham2019-06-211-1/+16
* [ARM] Add a batch of similarly encoded MVE instructions.Simon Tatham2019-06-211-1/+40
* [ARM] Add MVE vector compare instructions.Simon Tatham2019-06-211-2/+3
* [ARM] Add a batch of MVE floating-point instructions.Simon Tatham2019-06-211-4/+47
* [ARM] Add a batch of MVE integer instructions.Simon Tatham2019-06-201-1/+3
* [ARM] Add MVE vector bit-operations (register inputs).Simon Tatham2019-06-191-25/+126
* [ARM] Add MVE vector shift instructions.Simon Tatham2019-06-181-4/+41
* [ARM] Add MVE integer vector min/max instructions.Simon Tatham2019-06-181-1/+2
* [ARM] Rename MVE instructions in Tablegen for consistency.Simon Tatham2019-06-181-23/+23
* [ARM] Set up infrastructure for MVE vector instructions.Simon Tatham2019-06-131-65/+424
* [ARM] Refactor handling of IT mask operands.Simon Tatham2019-06-131-46/+37
* [ARM] First MVE instructions: scalar shifts.Mikhail Maltsev2019-06-111-0/+9
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-24/+273
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-111-1/+1
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-101-1/+1
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-101-273/+24
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-24/+273
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-15/+16
* [ARM] Create a TargetInfo header. NFCRichard Trieu2019-05-141-0/+1
* [ARM] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-112-2/+2
* ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover2019-04-231-0/+14
* Test commit accessOliver Stannard2019-04-111-0/+1
* [ARM][Asm] Accept upper case coprocessor number and registersOliver Stannard2019-03-261-2/+2
* Add XCOFF triple object format type for AIXJason Liu2019-03-121-0/+3
* Use bitset for assembler predicatesStanislav Mekhanoshin2019-03-111-53/+55
* [ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham2019-02-251-0/+12
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-192-8/+6
* [ARM][MC] Move information about variadic register defs into tablegenOliver Stannard2018-12-031-25/+1
* [ARM][Asm] Debug trace for the processInstruction loopOliver Stannard2018-12-031-1/+7
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