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path: root/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
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* [ARM][VecReduce] Force expand vector_reduce_fminDavid Green2020-02-051-3/+6
* [ARM] Expand vector reduction intrinsics on soft floatNikita Popov2020-02-051-1/+8
* [AArch64][ARM] Always expand ordered vector reductions (PR44600)Nikita Popov2020-02-051-1/+10
* [ARM][MVE] Enable masked gathers from vector of pointersAnna Welker2020-01-081-1/+1
* [ARM] Use isFMAFasterThanFMulAndFAdd for scalars as well as MVE vectorsDavid Green2020-01-051-9/+9
* [NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter]Anna Welker2019-12-181-0/+4
* Rename TTI::getIntImmCost for instructions and intrinsicsReid Kleckner2019-12-111-1/+1
* [ARM] Teach the Arm cost model that a Shift can be folded into other instruct...David Green2019-12-091-1/+2
* Revert "[ARM] Allocatable Global Register Variables for ARM"Carey Williams2019-11-291-3/+1
* [ARM] Allocatable Global Register Variables for ARMAnna Welker2019-11-181-1/+3
* [TTI][LV] preferPredicateOverEpilogueSjoerd Meijer2019-11-061-1/+6
* [Alignment][NFC] getMemoryOpCost uses MaybeAlignGuillaume Chatelet2019-10-251-1/+1
* [ARM][MVE] Enable truncating masked storesSam Parker2019-10-171-0/+1
* [NFC][TTI] Add Alignment for isLegalMasked[Load/Store]Sam Parker2019-10-141-2/+4
* recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure s...Zi Xuan Wu2019-10-121-1/+2
* Revert "[LoopVectorize][PowerPC] Estimate int and float register pressure sep...Jinsong Ji2019-10-081-2/+1
* [LoopVectorize][PowerPC] Estimate int and float register pressure separately ...Zi Xuan Wu2019-10-081-1/+2
* [ARM] Masked loads and storesDavid Green2019-09-151-0/+3
* [ARM] Remove MVE masked loads/storesDavid Green2019-09-011-14/+0
* [ARM] MVE Masked loads and storesDavid Green2019-08-291-0/+14
* [ARM] Add support for MVE vaddvSam Tebbs2019-08-191-0/+7
* [ARM] Permit auto-vectorization using MVEDavid Green2019-08-111-2/+6
* [NFC] move some hardware loop checking code to a common place for other using.Chen Zheng2019-06-191-1/+1
* [ARM] Implement TTI::isHardwareLoopProfitableSam Parker2019-06-121-0/+6
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-1/+1
* [ARM] Implement TTI::getMemcpyCostSjoerd Meijer2019-04-301-0/+2
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-1/+1
* [LSR] Generate cross iteration indexesSam Parker2019-02-071-0/+6
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-311-1/+3
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-141-1/+1
* revert 344472 due to failures.Dorit Nuzman2018-10-141-1/+1
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-141-1/+1
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-171-1/+1
* Remove trailing spaceFangrui Song2018-07-301-1/+1
* [Inliner] Restrict soft-float inlining penalty.Eli Friedman2017-12-221-2/+0
* [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use warnin...Eugene Zelenko2017-09-201-6/+21
* [ARM] Enable partial and runtime unrollingSam Parker2017-07-251-0/+3
* [ARM] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-07-131-0/+36
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-121-1/+1
* [SystemZ] TargetTransformInfo cost functions implemented.Jonas Paulsson2017-04-121-3/+5
* [TargetTransformInfo] Refactor and improve getScalarizationOverhead()Jonas Paulsson2017-01-261-4/+0
* [X86] updating TTI costs for arithmetic instructions on X86\SLM arch.Mohammed Agabaria2017-01-111-1/+2
* Currently isLikelyComplexAddressComputation tries to figure out if the given ...Mohammed Agabaria2017-01-051-1/+2
* Do a sweep over move ctors and remove those that are identical to the default.Benjamin Kramer2016-10-201-7/+0
* [ARM] Don't convert switches to lookup tables of pointers with ROPI/RWPIOliver Stannard2016-10-071-0/+10
* This implements a more optimal algorithm for selecting a base constant inSjoerd Meijer2016-07-141-0/+3
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 2). NFCIDiana Picus2016-06-271-4/+1
* [ARM] AArch32 v8 NEON is still not IEEE-754 compliantRenato Golin2016-04-181-1/+4
* ARM: don't try to hoist constant RHS out of a division.Tim Northover2016-04-151-3/+1
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