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* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-181-1/+1
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* Refactor the disabling of Thumb-1 LDM/STM generationJames Molloy2014-06-161-7/+3
| | | | | | | | Originally I switched the LD/ST optimizer off in TargetMachine as it was previously, but Eric has suggested he'd prefer that it be short-circuited in the pass itself. No functionality change. llvm-svn: 211037
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-151-1/+1
| | | | | | back. llvm-svn: 210996
* Remove InstrItineraryData off of the TargetMachine - it's alreadyEric Christopher2014-06-131-2/+1
| | | | | | on the subtarget and just forward the accessor. llvm-svn: 210955
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-131-1/+0
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-131-2/+0
| | | | llvm-svn: 210862
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-131-60/+2
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. llvm-svn: 210861
* Have ARMSelectionDAGInfo take a DataLayout as it's argument as theEric Christopher2014-06-121-2/+2
| | | | | | | DAG has access to the subtarget and TargetSelectionDAGInfo only needs a DataLayout. llvm-svn: 210859
* Disable the load/store optimization pass for Thumb-1.James Molloy2014-06-121-3/+7
| | | | | | | | Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out. Patch by Moritz Roth! llvm-svn: 210789
* ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover2014-05-301-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | The C and C++ semantics for compare_exchange require it to return a bool indicating success. This gets mapped to LLVM IR which follows each cmpxchg with an icmp of the value loaded against the desired value. When lowered to ldxr/stxr loops, this extra comparison is redundant: its results are implicit in the control-flow of the function. This commit makes two changes: it replaces that icmp with appropriate PHI nodes, and then makes sure earlyCSE is called after expansion to actually make use of the opportunities revealed. I've also added -{arm,aarch64}-enable-atomic-tidy options, so that existing fragile tests aren't perturbed too much by the change. Many of them either rely on undef/unreachable too pervasively to be restored to something well-defined (particularly while making sure they test the same obscure assert from many years ago), or depend on a particular CFG shape, which is disrupted by SimplifyCFG. rdar://problem/16227836 llvm-svn: 209883
* Enable the Load/Store optimization pass for Thumb1 but make it return ↵James Molloy2014-05-161-7/+4
| | | | | | | | immediately for now. Patch by Moritz Roth! llvm-svn: 208991
* Atomics: promote ARM's IR-based atomics pass to CodeGen.Tim Northover2014-04-171-1/+1
| | | | | | | | | | | | Still only 32-bit ARM using it at this stage, but the promotion allows direct testing via opt and is a reasonably self-contained patch on the way to switching ARM64. At this point, other targets should be able to make use of it without too much difficulty if they want. (See ARM64 commit coming soon for an example). llvm-svn: 206485
* ARM: expand atomic ldrex/strex loops in IRTim Northover2014-04-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded at MachineInstr emission time had grown to be extremely large and involved, to account for the subtly different code needed for the various flavours (8/16/32/64 bit, cmpxchg/add/minmax). Moving this transformation into the IR clears up the code substantially, and makes future optimisations much easier: 1. an atomicrmw followed by using the *new* value can be more efficient. As an IR pass, simple CSE could handle this efficiently. 2. Making use of cmpxchg success/failure orderings only has to be done in one (simpler) place. 3. The common "cmpxchg; did we store?" idiom can be exposed to optimisation. I intend to gradually improve this situation within the ARM backend and make sure there are no hidden issues before moving the code out into CodeGen to be shared with (at least ARM64/AArch64, though I think PPC & Mips could benefit too). llvm-svn: 205525
* Remove duplicated DMB instructionsRenato Golin2014-04-021-0/+1
| | | | | | | | | ARM specific optimiztion, finding places in ARM machine code where 2 dmbs follow one another, and eliminating one of them. Patch by Reinoud Elhorst. llvm-svn: 205409
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-011-16/+16
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* ARM: fix typoSaleem Abdulrasool2014-03-311-1/+1
| | | | llvm-svn: 205233
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-10/+57
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* Prune includes in ARM target.Craig Topper2014-03-221-1/+1
| | | | llvm-svn: 204548
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-5/+5
| | | | | | class. llvm-svn: 203433
* GlobalMerge: move "-global-merge" option to the pass itself.Tim Northover2014-02-181-6/+1
| | | | | | | It's rather odd to have the flag enabling and disabling this pass only affect a single target. llvm-svn: 201559
* Make the llvm mangler depend only on DataLayout.Rafael Espindola2014-01-031-2/+7
| | | | | | | | | | | | | | Before this patch any program that wanted to know the final symbol name of a GlobalValue had to link with Target. This patch implements a compromise solution where the mangler uses DataLayout. This way, any tool that already links with Target (llc, clang) gets the exact behavior as before and new IR files can be mangled without linking with Target. With this patch the mangler is constructed with just a DataLayout and DataLayout is extended to include the information the Mangler needs. llvm-svn: 198438
* Synchronize the NaCl DataLayout strings with the ones in clang.Rafael Espindola2013-12-191-2/+5
| | | | | | Patch by Derek Schuff. llvm-svn: 197640
* ARM: update comment to match realityTim Northover2013-12-181-1/+2
| | | | llvm-svn: 197570
* ARM: set default float ABI based on triple.Tim Northover2013-12-181-1/+2
| | | | | | | | | | | | Clang sets the float-abi target option manually, but no longer annotates each function with its ABI. This can lead to confusing mistmatch between "clang -emit-llvm | llc" and normal clang invocations. Besides which, gnueabihf actually *is* hard-float. Defaulting to soft was just perverse. llvm-svn: 197554
* On APCS, only try to align aggregates to 32 bits instead of 64.Rafael Espindola2013-12-171-3/+3
| | | | | | | This matches clang's behavior and since it is only a preference, it is not an ABI issue. llvm-svn: 197526
* Handle i64 first for clarity. No functionality change.Rafael Espindola2013-12-171-5/+6
| | | | llvm-svn: 197524
* One last cleanup of LLVM's DataLayout strings.Rafael Espindola2013-12-161-6/+6
| | | | | | | Produce them in the same order on every target. The order is that of getStringRepresentation: e|E-i*-f*-v*-a*-s*-n*-S*. llvm-svn: 197411
* The preferred alignment defaults to the abi alignment. Omit if it is the same.Rafael Espindola2013-12-161-1/+1
| | | | llvm-svn: 197400
* Simplify the datalayout string of ARM and AArch64.Rafael Espindola2013-12-121-3/+3
| | | | | | | | No functionality change. Reviewed by Tim Northover. llvm-svn: 197172
* Add comments documenting the ARM datalayout string.Rafael Espindola2013-12-101-0/+12
| | | | llvm-svn: 196850
* Simplify further.Rafael Espindola2013-12-101-12/+4
| | | | | | Thanks to Jim Grosbach for noticing it. llvm-svn: 196846
* Refactor the construction of the DataLayout string on ARM.Rafael Espindola2013-12-091-19/+39
| | | | llvm-svn: 196843
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-131-1/+1
| | | | | | | | | | | | | | By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. llvm-svn: 194592
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-091-1/+6
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The ↵Silviu Baranga2013-07-291-1/+1
| | | | | | patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4. llvm-svn: 187349
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184352
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-1/+1
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184349
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+2
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Enabling the generation of dependency breakers for partial updates on ↵Silviu Baranga2013-03-271-2/+1
| | | | | | Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32. llvm-svn: 178134
* Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin2013-03-211-1/+1
| | | | | | | | | | NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. llvm-svn: 177651
* Adding an A15 specific optimization pass for interactions between S/D/Q ↵Silviu Baranga2013-03-151-1/+13
| | | | | | registers. The pass handles all the required transformations pre-regalloc. llvm-svn: 177169
* ARM: Fix a few copy-paste errors.Jim Grosbach2013-01-071-2/+2
| | | | | | s/X86/ARM/ llvm-svn: 171789
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-071-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Remove TargetELFWriterInfo.Rafael Espindola2012-10-281-2/+0
| | | | | | All the credit goes to Jan Voung for noticing it was dead! llvm-svn: 166902
* Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem2012-10-241-2/+2
| | | | | | and bb vectorizers for modeling the cost of instructions. llvm-svn: 166593
* Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem2012-10-181-2/+4
| | | | | | Lowerinvoke. llvm-svn: 166248
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-181-4/+2
| | | | | | | | | | | The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 llvm-svn: 166168
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-101-2/+4
| | | | | | information. llvm-svn: 165665
* Move TargetData to DataLayout.Micah Villmow2012-10-081-2/+2
| | | | llvm-svn: 165402
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