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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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* initial support for variable number of argumentsRafael Espindola2006-08-081-8/+17
| | | | llvm-svn: 29567
* implemented subRafael Espindola2006-07-211-3/+8
| | | | | | correctly update the stack pointer in the prologue and epilogue llvm-svn: 29244
* initial prologue and epilogue implementation. Need to define add and sub ↵Rafael Espindola2006-07-181-0/+20
| | | | | | before finishing it :-) llvm-svn: 29175
* add the memri memory operandRafael Espindola2006-07-111-8/+18
| | | | | | this makes it possible for ldr instructions with non-zero immediate llvm-svn: 29103
* create the raddr addressing mode that matches any register and the frame indexRafael Espindola2006-07-101-1/+1
| | | | | | | | | use raddr for the ldr instruction. This removes a dummy mov from the assembly output remove SelectFrameIndex remove isLoadFromStackSlot remove isStoreToStackSlot llvm-svn: 29079
* handle the "mov reg1, reg2" case in isMoveInstrRafael Espindola2006-06-271-1/+1
| | | | llvm-svn: 28945
* initial implementation of ARMRegisterInfo::eliminateFrameIndexRafael Espindola2006-06-181-1/+23
| | | | | | fixes test/Regression/CodeGen/ARM/ret_arg5.ll llvm-svn: 28854
* implement movriRafael Espindola2006-05-181-1/+1
| | | | | | add a stub LowerFORMAL_ARGUMENTS llvm-svn: 28388
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+11
| | | | llvm-svn: 28378
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+91
llvm-svn: 28301
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