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path: root/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
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* Fix Thumb2 fixups for ldr.Owen Anderson2010-12-091-1/+7
| | | | llvm-svn: 121350
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-091-12/+16
| | | | | | | | | | particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. llvm-svn: 121336
* Fix Thumb2 BCC encoding and fixups.Owen Anderson2010-12-091-0/+4
| | | | llvm-svn: 121329
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-081-28/+33
| | | | llvm-svn: 121308
* Add support for loading from a constant pool.Bill Wendling2010-12-081-3/+27
| | | | llvm-svn: 121226
* VLDR fixups need special handling under Thumb. While the encoding is the same,Owen Anderson2010-12-081-1/+7
| | | | | | the order of the bytes in the data stream is flipped around. llvm-svn: 121215
* Fix a warning about a variable which is only used in an assertion.Matt Beaumont-Gay2010-12-071-2/+2
| | | | llvm-svn: 121206
* Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach2010-12-071-0/+19
| | | | llvm-svn: 121186
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-3/+8
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-061-0/+24
| | | | llvm-svn: 121072
* Encode the 32-bit wide Thumb (and Thumb2) instructions with the high orderJim Grosbach2010-12-031-1/+9
| | | | | | halfword being emitted to the stream first. rdar://8728174 llvm-svn: 120848
* The tLDR instruction wasn't encoded properly:Bill Wendling2010-12-031-2/+6
| | | | | | | | | <MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>> Notice that the "reg" here is 0, which is an invalid register. Put a check in the code for this to prevent crashing. llvm-svn: 120766
* Add support for binary encoding of ARM 'adr' instructions referencing constantJim Grosbach2010-12-021-13/+10
| | | | | | pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
* Add a post encoder method to the VFP instructions to convert them to the Thumb2Bill Wendling2010-12-011-3/+15
| | | | | | encoding if we're in that mode. llvm-svn: 120608
* Use the correct fixup type for ARM VLDR*Jim Grosbach2010-12-011-2/+2
| | | | llvm-svn: 120604
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-011-0/+23
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-2/+42
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* 10 bits, not 12.Jim Grosbach2010-12-011-2/+2
| | | | llvm-svn: 120584
* Fix typo.Jim Grosbach2010-11-301-1/+1
| | | | llvm-svn: 120499
* Thanks to JimG for catching this!Jason W Kim2010-11-301-0/+2
| | | | llvm-svn: 120494
* * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling2010-11-301-5/+33
| | | | | | | | | | t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. llvm-svn: 120482
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-301-15/+0
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* Fix handling of ARM negative pc-relative fixups for loads and stores.Jim Grosbach2010-11-301-4/+9
| | | | llvm-svn: 120480
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-301-0/+18
| | | | llvm-svn: 120449
* Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling2010-11-301-0/+24
| | | | | | | | | | certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. llvm-svn: 120408
* Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson2010-11-301-2/+24
| | | | llvm-svn: 120364
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-301-0/+28
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. llvm-svn: 120358
* Provide Thumb2 encodings for basic loads and stores.Owen Anderson2010-11-291-0/+55
| | | | llvm-svn: 120340
* Fix a compiler warning about Kind being used uninitializedDuncan Sands2010-11-221-1/+1
| | | | | | when assertions are disabled. llvm-svn: 119962
* Minor cleanups to a few llvm_unreachable() calls.Jim Grosbach2010-11-191-6/+3
| | | | llvm-svn: 119767
* An 'unreachable' shouldn't have a '0 &&' prefix.Bill Wendling2010-11-191-2/+2
| | | | llvm-svn: 119762
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-181-0/+31
| | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
* Add binary emission stuff for VLDM/VSTM. This reuses theBill Wendling2010-11-171-5/+26
| | | | | | | "getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. llvm-svn: 119435
* ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach2010-11-151-16/+61
| | | | llvm-svn: 119180
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-1/+1
| | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. llvm-svn: 119120
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-121-0/+52
| | | | llvm-svn: 118924
* Start of support for binary emit of 16-it Thumb instructions.Jim Grosbach2010-11-111-3/+10
| | | | llvm-svn: 118859
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-111-0/+17
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-111-1/+18
| | | | llvm-svn: 118843
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-111-0/+23
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-111-3/+28
| | | | | | instructions. llvm-svn: 118801
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-111-0/+23
| | | | llvm-svn: 118794
* ARM STRH encoding information.Jim Grosbach2010-11-111-1/+26
| | | | llvm-svn: 118757
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-101-0/+13
| | | | llvm-svn: 118736
* For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach2010-11-091-0/+3
| | | | | | a left shift by zero. llvm-svn: 118587
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-091-0/+45
| | | | llvm-svn: 118513
* Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach2010-11-091-8/+2
| | | | | | | | | | | | | | constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. llvm-svn: 118469
* Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling2010-11-091-5/+8
| | | | llvm-svn: 118462
* Get the register and count from the register list operands.Bill Wendling2010-11-081-8/+5
| | | | llvm-svn: 118458
* Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach2010-11-041-30/+51
| | | | | | | tweaking when we start using it for object file emission or JIT, but it's a start. llvm-svn: 118221
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