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path: root/llvm/lib/Target/ARM/ARMInstrThumb2.td
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* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-081-6/+3
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-39/+154
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-154/+39
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-39/+154
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-01-071-3/+6
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-201-6/+3
* [ARM][MVE] Fixes for tail predication.Sam Parker2019-12-201-4/+6
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-191-3/+6
* [ARM] Generate CMSE instructions from CMSE intrinsicsMomchil Velikov2019-11-251-4/+12
* [ARM] Extra qdadd patternsDavid Green2019-10-211-0/+4
* [ARM] Add qadd lowering from a sadd_satDavid Green2019-10-211-0/+4
* [ARM] Lower sadd_sat to qadd8 and qadd16David Green2019-10-211-0/+9
* [ARM] Cortex-M4 schedule additionsDavid Green2019-09-291-1/+2
* [ARM] Ensure we do not attempt to create lsll #0David Green2019-09-251-1/+2
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-24/+24
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-24/+24
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-24/+24
* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-031-0/+19
* [ARM] Reject CSEL instructions with invalid operandsMikhail Maltsev2019-07-311-1/+1
* [ARM][LowOverheadLoops] Add CPSR defsSam Parker2019-07-261-2/+4
* [ARM] MVE bitwise instruction patternsDavid Green2019-07-041-1/+2
* [ARM] WLS/LE Code GenerationSam Parker2019-07-011-1/+9
* [ARM] Fix handling of zero offsets in LOB instructions.Simon Tatham2019-06-271-8/+9
* [ARM] Tighten restrictions on use of SP in v8.1-M CSEL.Simon Tatham2019-06-271-4/+4
* [ARM] Add remaining miscellaneous MVE instructions.Simon Tatham2019-06-251-2/+21
* [ARM] Add MVE vector load/store instructions.Simon Tatham2019-06-251-6/+15
* [ARM] DLS/LE low-overhead loop code generationSam Parker2019-06-251-0/+16
* [ARM] Add MVE interleaving load/store family.Simon Tatham2019-06-241-2/+2
* [ARM] Refactor handling of IT mask operands.Simon Tatham2019-06-131-0/+1
* [ARM] First MVE instructions: scalar shifts.Mikhail Maltsev2019-06-111-0/+10
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-1/+298
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-101-298/+1
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-17/+7
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-101-1/+308
* [ARM] Turn some undefined encoding bits into 0s.Simon Tatham2019-06-041-0/+17
* [ARM] Cortex-M4 scheduleDavid Green2019-05-151-25/+27
* ARM: disallow SP as Rn for Thumb2 TST & TEQ instructionsTim Northover2019-05-081-14/+14
* [ARM] Add v8m.base pattern for add negative immSam Parker2019-02-111-0/+5
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] Add missing patterns for DSP mulsSam Parker2019-01-081-25/+20
* [ARM] Add command-line option for SBDiogo N. Sampaio2019-01-031-1/+1
* ARM: use acquire/release instruction variants when available.Tim Northover2018-12-171-7/+7
* ARM: use target-specific SUBS node when combining cmp with cmov.Tim Northover2018-12-031-0/+6
* [ARM][MC] Move information about variadic register defs into tablegenOliver Stannard2018-12-031-1/+1
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-281-0/+6
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-271-0/+8
* ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.Tim Northover2018-09-071-2/+2
* [ARM] Rotated operand patterns for *xtb16Sam Parker2018-08-221-0/+8
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-061-0/+6
* [ARM] [Assembler] Support negative immediates: cover few missing casesVolodymyr Turanskyy2018-07-041-0/+18
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