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* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-4/+5
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Remove DefInst from LiveVariables::VarInfo. Use the facilities on ↵Owen Anderson2008-01-151-3/+0
| | | | | | MachineRegisterInfo instead. llvm-svn: 46016
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-2/+2
| | | | llvm-svn: 45871
* Only mark instructions that load a single value without extension as ↵Evan Cheng2008-01-071-1/+1
| | | | | | isSimpleLoad = 1. llvm-svn: 45727
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-11/+11
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename all the M_* flags to be namespace qualified enums, and switch Chris Lattner2008-01-071-1/+1
| | | | | | | | all clients over to using predicates instead of these flags directly. These are now private values which are only to be used to statically initialize the tables. llvm-svn: 45692
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-3/+3
| | | | llvm-svn: 45680
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45679
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-6/+6
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+113
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45667
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-0/+45
| | | | llvm-svn: 45603
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+128
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+38
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-12/+12
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-10/+10
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* use simplified operand addition methods.Chris Lattner2007-12-301-2/+2
| | | | llvm-svn: 45437
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman2007-09-141-3/+3
| | | | | | | isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. llvm-svn: 41958
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* ARM: make branch folder remove unconditional branchesDale Johannesen2007-07-121-2/+13
| | | | | | | | following jump tables that it earlier inserted. This would be OK on other targets but is needed for correctness only on ARM (constant islands needs to find jump tables). llvm-svn: 39782
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-5/+29
| | | | | | the 's' bit. llvm-svn: 38501
* Incorrect check.Evan Cheng2007-07-061-4/+2
| | | | llvm-svn: 37962
* Reflects the chanegs made to PredicateOperand.Evan Cheng2007-07-051-4/+10
| | | | llvm-svn: 37898
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-14/+0
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-0/+14
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-29/+0
| | | | llvm-svn: 37643
* Instructions with unique labels or embedded jumptables cannot be duplicated ↵Evan Cheng2007-06-151-0/+29
| | | | | | during ifcvt. llvm-svn: 37606
* Handle blocks with 2 unconditional branches in AnalyzeBranch.Dale Johannesen2007-06-131-0/+10
| | | | llvm-svn: 37571
* Add a utility routine to check for unpredicated terminator instruction.Evan Cheng2007-06-081-3/+3
| | | | llvm-svn: 37528
* Fix ARM condition code subsumission check.Evan Cheng2007-06-081-3/+3
| | | | llvm-svn: 37517
* Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a ↵Evan Cheng2007-06-071-1/+1
| | | | | | compilation warning? I blame it on the FE folks. llvm-svn: 37484
* Add missing const qualifiers.Evan Cheng2007-05-291-9/+11
| | | | llvm-svn: 37342
* Hooks for predication support.Evan Cheng2007-05-231-8/+33
| | | | llvm-svn: 37308
* Fix some -march=thumb regressions. tBR_JTr is not predicable.Evan Cheng2007-05-211-1/+3
| | | | llvm-svn: 37272
* BlockHasNoFallThrough() now returns true if block ends with a return ↵Evan Cheng2007-05-211-2/+13
| | | | | | instruction; AnalyzeBranch() should ignore predicated instructionsd. llvm-svn: 37268
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-7/+9
| | | | | | / inserted. llvm-svn: 37193
* PredicateInstruction returns true if the operation was successful.Evan Cheng2007-05-161-3/+7
| | | | llvm-svn: 37124
* Removed isPredicable().Evan Cheng2007-05-161-9/+0
| | | | llvm-svn: 37119
* Hooks for predication support.Evan Cheng2007-05-161-0/+22
| | | | llvm-svn: 37093
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-16/+21
| | | | llvm-svn: 37066
* Rewrite of Thumb constant islands handling (exact allowance for paddingDale Johannesen2007-04-291-3/+4
| | | | | | around islands and jump tables). llvm-svn: 36573
* Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng2007-04-261-1/+1
| | | | llvm-svn: 36483
* Relex assertions to account for additional implicit def / use operands.Evan Cheng2007-04-251-1/+1
| | | | llvm-svn: 36430
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-161-2/+2
| | | | | | target for tabs checking. llvm-svn: 36146
* Inverted logic.Evan Cheng2007-04-031-1/+1
| | | | llvm-svn: 35619
* findRegisterUseOperand() changed.Evan Cheng2007-03-261-2/+2
| | | | llvm-svn: 35366
* Fix naming inconsistencies.Evan Cheng2007-03-191-2/+2
| | | | llvm-svn: 35163
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