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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* Reduce indentation.Bob Wilson2010-06-251-8/+7
* Do not do tail calls to external symbols. If theDale Johannesen2010-06-231-12/+9
* When using libcall expansions for the atomic intrinsics, the explicitJim Grosbach2010-06-231-0/+2
* sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.Bob Wilson2010-06-211-1/+1
* Fix error message to match function name.Bob Wilson2010-06-191-1/+1
* Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emi...Evan Cheng2010-06-191-8/+17
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-181-0/+4
* Enable Expand handling of atomics for subtargets that can't do them inline.Jim Grosbach2010-06-181-3/+39
* Enable tail calls on ARM by default, with someDale Johannesen2010-06-181-1/+1
* Last round of changes for ARM tail calls.Dale Johannesen2010-06-181-7/+14
* Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86Jakob Stoklund Olesen2010-06-181-1/+1
* Thumb1 and any pre-v6 ARM target should use the libcall expansion ofJim Grosbach2010-06-171-1/+6
* simplify code a bit and add a more explanatory assert for cases thatJim Grosbach2010-06-171-15/+11
* format and 80-column cleanupJim Grosbach2010-06-161-5/+4
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-4/+1
* Make post-ra scheduling, anti-dep breaking, and register scavenger (conservat...Evan Cheng2010-06-161-1/+6
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-5/+8
* Add basic support for NEON modified immediates besides VMOV.Bob Wilson2010-06-151-4/+15
* Rename functions referring to VMOV immediates to refer to NEON "modifiedBob Wilson2010-06-141-17/+21
* Add a missing bitcast. This code used to only handle conversions betweenBob Wilson2010-06-111-1/+2
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-26/+89
* Further changes for Neon vector shuffles:Bob Wilson2010-06-071-52/+56
* Improvements to tail call code. No functional effectDale Johannesen2010-06-051-20/+22
* More thoroughly disable tails calls by default.Dale Johannesen2010-06-041-3/+3
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-041-19/+16
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-6/+230
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-3/+4
* Schedule high latency instructions for latency reduction even if they are not...Evan Cheng2010-05-281-1/+19
* Update the saved stack pointer in the sjlj function context following eitherJim Grosbach2010-05-271-5/+1
* back out 104862/104869. Can reuse stacksave after all. Very cool.Jim Grosbach2010-05-271-8/+0
* add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EHJim Grosbach2010-05-271-0/+8
* Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry inJim Grosbach2010-05-261-6/+12
* Clean up indentation.Bob Wilson2010-05-251-2/+2
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-241-4/+1
* VDUP doesn't support vectors with 64-bit elements.Bob Wilson2010-05-231-2/+2
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-2/+27
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-221-0/+9
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-221-29/+72
* Change ARM scheduling default to list-hybrid if the target supports floating ...Evan Cheng2010-05-211-1/+4
* Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng2010-05-201-0/+10
* Handle Neon v2f64 and v2i64 vector shuffles as register copies.Bob Wilson2010-05-201-0/+18
* Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMa...Evan Cheng2010-05-191-1/+1
* Sink dag combine's post index load / store code that swap base ptr and index ...Evan Cheng2010-05-181-1/+15
* Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.Anton Korobeynikov2010-05-161-34/+21
* Some cheap DAG combine goodness for multiplication with a particular constant.Anton Korobeynikov2010-05-151-0/+71
* v4i64 and v8i64 are only synthesizable when NEON is available.Evan Cheng2010-05-151-4/+6
* Allow TargetLowering::getRegClassFor() to be called on illegal types. AlsoEvan Cheng2010-05-151-7/+13
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-1/+3
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-111-110/+0
* Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.Evan Cheng2010-05-111-0/+2
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