diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2010-05-15 02:18:07 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-15 02:18:07 +0000 |
| commit | 4cad68eb346fee721e4638b231864bc79b638221 (patch) | |
| tree | 406622143150ba4d50989d48877e86eb1881261d /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 749dc33dff5905b1567d6d529ba4e38e3e5148fd (diff) | |
| download | bcm5719-llvm-4cad68eb346fee721e4638b231864bc79b638221.tar.gz bcm5719-llvm-4cad68eb346fee721e4638b231864bc79b638221.zip | |
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
llvm-svn: 103854
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 529f7115f5b..9db641172d7 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -266,13 +266,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) addQRTypeForNEON(MVT::v4i32); addQRTypeForNEON(MVT::v2i64); - // Map v4i64 to QQ registers but do not make the type legal for any - // operations. Similarly map v8i64 to QQQQ registers. v4i64 and v8i64 are - // only used for REG_SEQUENCE to load / store 4 to 8 consecutive - // D registers. - addRegisterClass(MVT::v4i64, ARM::QQPRRegisterClass); - addRegisterClass(MVT::v8i64, ARM::QQQQPRRegisterClass); - // v2f64 is legal so that QR subregs can be extracted as f64 elements, but // neither Neon nor VFP support any arithmetic operations on it. setOperationAction(ISD::FADD, MVT::v2f64, Expand); @@ -586,6 +579,19 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { } } +/// getRegClassFor - Return the register class that should be used for the +/// specified value type. +TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { + // Map v4i64 to QQ registers but do not make the type legal. Similarly map + // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to + // load / store 4 to 8 consecutive D registers. + if (VT == MVT::v4i64) + return ARM::QQPRRegisterClass; + else if (VT == MVT::v8i64) + return ARM::QQQQPRRegisterClass; + return TargetLowering::getRegClassFor(VT); +} + /// getFunctionAlignment - Return the Log2 alignment of this function. unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1; |

