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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-27/+36
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-171-12/+18
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that thisBob Wilson2010-04-171-12/+22
| | | | | | | | | may be called when either the source or destination type is i64, and my change also hadn't fixed the most obvious problem -- assuming that i64 will only be bitconverted to f64, ignoring the various vector types. Radar 7873160. llvm-svn: 101615
* Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle ↵Evan Cheng2010-04-151-4/+1
| | | | | | is doing the right thing and codegen looks correct for both Thumb and Thumb2. llvm-svn: 101410
* Fix build.Anders Carlsson2010-04-151-1/+1
| | | | llvm-svn: 101335
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-6/+6
| | | | llvm-svn: 101334
* Add -arm-long-calls option to force calls to be indirect. This makes theJim Grosbach2010-04-141-2/+44
| | | | | | | | kernel linker happier when dealing with kexts. Radar 7805069 llvm-svn: 101303
* Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operandBob Wilson2010-04-141-9/+16
| | | | | | | does not have a legal type. The legalizer does not know how to handle those nodes. Radar 7854640. llvm-svn: 101282
* Handle a v2f64 formal parameter that is split between registers and memoryBob Wilson2010-04-131-7/+13
| | | | | | such that the entire second half is in memory. Radar 7855014. llvm-svn: 101181
* Expand SELECT and SELECT_CC for NEON vector types.Bob Wilson2010-04-061-0/+2
| | | | | | Radar 7770501. llvm-svn: 100568
* Reapply address space patch after fixing an issue in MemCopyOptimizer.Mon P Wang2010-04-041-4/+5
| | | | | | | Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) llvm-svn: 100304
* Revert r100191 since it breaks objc in clang Mon P Wang2010-04-021-5/+4
| | | | llvm-svn: 100199
* Reapply address space patch after fixing an issue in MemCopyOptimizer.Mon P Wang2010-04-021-4/+5
| | | | | | | Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) llvm-svn: 100191
* Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.Bob Wilson2010-03-301-5/+4
| | | | llvm-svn: 99948
* Added support for address spaces and added a isVolatile field to memcpy, ↵Mon P Wang2010-03-301-4/+5
| | | | | | | | | memmove, and memset, e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) A update of langref will occur in a subsequent checkin. llvm-svn: 99928
* tweak the arm if conversion heuristicJim Grosbach2010-03-241-7/+1
| | | | llvm-svn: 99402
* try being more permissive for if-conversion on ARM V7. see what the nightlyJim Grosbach2010-03-241-0/+9
| | | | | | test run permformance numbers say as to whether it helps. llvm-svn: 99355
* Revert this change, since it was causing ARM performance regressions.Bob Wilson2010-03-191-0/+54
| | | | | | | | | | | | --- Reverse-merging r98889 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMISelLowering.h U lib/Target/ARM/ARMInstrInfo.td U lib/Target/ARM/ARMInstrVFP.td U lib/Target/ARM/ARMISelLowering.cpp U lib/Target/ARM/ARMInstrFormats.td llvm-svn: 99010
* Get rid of target-specific fp <-> int nodes when still I'm here.Anton Korobeynikov2010-03-181-54/+0
| | | | llvm-svn: 98889
* Get rid of target-specific nodes for fp16 <-> fp32 conversion.Anton Korobeynikov2010-03-181-13/+3
| | | | llvm-svn: 98888
* Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass.Bob Wilson2010-03-151-0/+3
| | | | | | Radar 7459078. llvm-svn: 98586
* Now that the default for Darwin platforms is to place the LSDA into the TEXTBill Wendling2010-03-151-1/+1
| | | | | | section, remove the target-specific code that performs this. llvm-svn: 98580
* Add substarget feature for FP16Anton Korobeynikov2010-03-141-1/+1
| | | | llvm-svn: 98503
* Add codegen support for FP16 on ARMAnton Korobeynikov2010-03-141-10/+48
| | | | llvm-svn: 98502
* The ARM EH experiment worked!Bill Wendling2010-03-091-30/+1
| | | | | | | | | | | | Place the LSDA into the TEXT section for ARM platforms. This involves making the encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The references to the type infos are then non-lazy pointers. Revision 98019 changed the encoding of non-lazy pointers to add the symbol to the non-lazy pointer definition if it's a local symbol (otherwise, it's external and set to '0' so that the loader can adjust it to the real value). This paved the way for this change to work on ARM. llvm-svn: 98068
* This is part of an LLC-beta test used to test <rdar://problem/6804645>. PleaseBill Wendling2010-03-091-1/+31
| | | | | | bear with the awful code. It won't last in its current state beyond tonight. llvm-svn: 98040
* Remove dead parameter passing.Bill Wendling2010-03-021-2/+1
| | | | llvm-svn: 97536
* Check for comparisons of +/- zero when optimizing less-than-or-equal andBob Wilson2010-02-241-22/+31
| | | | | | | | greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is only allowed when UnsafeFPMath is set or when at least one of the operands is known to be nonzero. llvm-svn: 97065
* LowerCall() should always do getCopyFromReg() to reference the stack pointer.Jim Grosbach2010-02-241-5/+1
| | | | | | | Machine instruction selection is much happier when operands are in virtual registers. llvm-svn: 97012
* Use NEON vmin/vmax instructions for floating-point selects.Bob Wilson2010-02-181-8/+85
| | | | | | Radar 7461718. llvm-svn: 96572
* Remove an assumption of default arguments. This is in anticipation of aDavid Greene2010-02-151-28/+49
| | | | | | change to SelectionDAG build APIs. llvm-svn: 96230
* tighten up eh.setjmp sequence a bit.Jim Grosbach2010-02-081-3/+9
| | | | llvm-svn: 95603
* Revert 95130.Evan Cheng2010-02-021-1/+1
| | | | llvm-svn: 95160
* Pass callsite return type to TargetLowering::LowerCall and use that to check ↵Evan Cheng2010-02-021-1/+1
| | | | | | sibcall eligibility. llvm-svn: 95130
* Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.Anton Korobeynikov2010-01-301-2/+5
| | | | | | | | | Even if they are suported by the core, they can be disabled (this is just a configuration bit inside some register). Allow unaligned memops on darwin and conservatively disallow them otherwise. llvm-svn: 94889
* Eliminate target hook IsEligibleForTailCallOptimization.Evan Cheng2010-01-271-1/+3
| | | | | | | | | Target independent isel should always pass along the "tail call" property. Change target hook LowerCall's parameter "isTailCall" into a refernce. If the target decides it's impossible to honor the tail call request, it should set isTailCall to false to make target independent isel happy. llvm-svn: 94626
* Wrap some comments to 80 columns.Bob Wilson2010-01-191-2/+4
| | | | llvm-svn: 93940
* Patch by David Conrad:Jim Grosbach2010-01-181-1/+16
| | | | | | | "On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction sequence it is now." llvm-svn: 93758
* Name change for consistency. No functional change.Jim Grosbach2010-01-151-7/+7
| | | | llvm-svn: 93480
* EmitAtomicCmpSwap() custome inserter needs to delete the MI passed in. ↵Jim Grosbach2010-01-151-0/+3
| | | | | | EmitAtomicBinary() already does this. llvm-svn: 93479
* ARM "l" constraint for inline asm means R0-R7, also for Thumb2.Jakob Stoklund Olesen2010-01-141-2/+2
| | | | | | | | | This is consistent with llvm-gcc's arm/constraints.md. Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2 mode. llvm-svn: 93436
* Fix pastoJakob Stoklund Olesen2010-01-131-1/+1
| | | | llvm-svn: 93342
* Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling2009-12-221-1/+2
| | | | | | | | return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. llvm-svn: 91880
* Delete the instruction just before the function terminates for consistency sake.Evan Cheng2009-12-211-2/+3
| | | | llvm-svn: 91836
* Fix libstdc++ build on ARM linux and part of PR5770.Rafael Espindola2009-12-181-0/+3
| | | | | | | | | | | | | | MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done. Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts. For a patch that make us detect problems like this earlier, take a look at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html With that patch we assert as soon and the new instruction is added to the garbage set. llvm-svn: 91691
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-2/+2
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* nand atomic requires opposite operand orderingJim Grosbach2009-12-151-3/+9
| | | | llvm-svn: 91371
* Add ARMv6 memory and sync barrier instructionsJim Grosbach2009-12-141-6/+13
| | | | llvm-svn: 91329
* Thumb2 atomic operationsJim Grosbach2009-12-141-44/+83
| | | | llvm-svn: 91321
* atomic binary operations up to 32-bits wide.Jim Grosbach2009-12-141-5/+63
| | | | llvm-svn: 91260
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