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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* whitespaceAndrew Trick2011-09-201-13/+13
| | | | llvm-svn: 140133
* Thumb2 assembly parsing and encoding for STR.Jim Grosbach2011-09-161-0/+13
| | | | | | | More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH and STR(register). llvm-svn: 139949
* Minor cleanup.Eli Friedman2011-09-151-3/+2
| | | | llvm-svn: 139869
* Use a more efficient lowering for Unordered/Monotonic atomic load/store on ↵Eli Friedman2011-09-151-2/+18
| | | | | | Thumb1. llvm-svn: 139865
* Tidy up a few 80 column violations.Jim Grosbach2011-09-131-2/+3
| | | | llvm-svn: 139636
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-2/+4
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-9/+24
| | | | llvm-svn: 139381
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-5/+12
| | | | | | | | | | | | with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
* Fix fall outs from my recent change on how carry bit is modeled during isel.Evan Cheng2011-09-061-1/+1
| | | | | | | | Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 llvm-svn: 139157
* Null-initialize to shut up -Wuninitialized warnings.Eli Friedman2011-09-011-1/+1
| | | | llvm-svn: 138974
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-311-27/+74
| | | | llvm-svn: 138868
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-311-0/+179
| | | | llvm-svn: 138845
* Follow up to r138791.Evan Cheng2011-08-301-0/+23
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-301-73/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well ↵Eli Friedman2011-08-291-0/+1
| | | | | | enough to fix properly. llvm-svn: 138751
* Silence GCC warnings and make an array const.Benjamin Kramer2011-08-271-3/+3
| | | | llvm-svn: 138706
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-261-0/+2
| | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. llvm-svn: 138621
* ARM expansion of pre-indexed store pseudos should maintain memoperands.Jim Grosbach2011-08-121-1/+3
| | | | | | Partial fix for rdar://9945172. llvm-svn: 137513
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-2/+2
| | | | | | when building with assertions disabled. llvm-svn: 137460
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-111-3/+9
| | | | llvm-svn: 137353
* ARM fix typo in pre-indexed store lowering.Jim Grosbach2011-08-091-1/+1
| | | | | | rdar://9915869 llvm-svn: 137148
* ARM refactor indexed store instructions.Jim Grosbach2011-08-051-0/+31
| | | | | | | | | | Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
* New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman2011-08-031-78/+9
| | | | | | | | platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. llvm-svn: 136813
* ARM backend support for atomicrmw and cmpxchg with non-monotonic ordering. ↵Eli Friedman2011-08-021-47/+77
| | | | | | Not especially pretty, but seems to work well enough. If this looks okay, I'll put together similar patches for Mips, PPC, and Alpha. llvm-svn: 136737
* Add support for the 'Q' constraint.Eric Christopher2011-07-291-0/+3
| | | | | | Fixes rdar://9866494 llvm-svn: 136523
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+30
| | | | llvm-svn: 136283
* ARM extend instructions simplification.Jim Grosbach2011-07-271-3/+5
| | | | | | | | Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. llvm-svn: 136225
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-211-4/+8
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-2/+3
| | | | | | ARM MC code from target. llvm-svn: 135636
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-6/+6
| | | | llvm-svn: 135375
* Improve codegen for select's:Evan Cheng2011-07-131-1/+66
| | | | | | | | | | | | | | | | | | | | if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+3
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
* Add more info to FIXME.Jim Grosbach2011-07-081-1/+5
| | | | llvm-svn: 134729
* ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-011-1/+2
| | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 llvm-svn: 134261
* Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher2011-07-011-0/+9
| | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 llvm-svn: 134222
* Add support for the ARM 't' register constraint. And another testcaseEric Christopher2011-07-011-0/+5
| | | | | | | | for the 'x' register constraint. Part of rdar://9119939 llvm-svn: 134220
* We'll return a null RC by default if we can't match.Eric Christopher2011-07-011-2/+1
| | | | | | Part of rdar://9119939 llvm-svn: 134217
* Add support for the 'x' constraint.Eric Christopher2011-07-011-0/+9
| | | | | | Part of rdar://9307836 and rdar://9119939 llvm-svn: 134215
* Capitalize the unsigned part of the initializer.Eric Christopher2011-06-301-1/+1
| | | | llvm-svn: 134211
* Rename Pair to RCPair lacking any better naming ideas.Eric Christopher2011-06-301-10/+10
| | | | llvm-svn: 134210
* Add support for the 'h' constraint.Eric Christopher2011-06-301-1/+7
| | | | | | Part of rdar://9119939 llvm-svn: 134203
* Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher2011-06-301-7/+8
| | | | | | | | No functional change. Part of rdar://9119939 llvm-svn: 134198
* Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher2011-06-291-56/+15
| | | | | | Part of rdar://9643582 llvm-svn: 134095
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-3/+3
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Remove warning: 'c0' may be used uninitialized in this function.Chad Rosier2011-06-281-1/+2
| | | | llvm-svn: 134014
* The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier2011-06-241-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 llvm-svn: 133813
* Handle the memory-ness of all U+ ARM constraints.Eric Christopher2011-06-211-3/+6
| | | | | | Noticed on inspection. llvm-svn: 133553
* Remove unused but set variables.Benjamin Kramer2011-06-181-1/+0
| | | | llvm-svn: 133347
* Mark ldrexd/strexd w/ volatile memory by defaultBruno Cardoso Lopes2011-06-161-2/+2
| | | | llvm-svn: 133175
* Revision r128665 added an optimization to make use of NEON multiplierChad Rosier2011-06-161-1/+1
| | | | | | | | | | | | | | | | | accumulator forwarding. Specifically (from SVN log entry): Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was intended in the original revision. llvm-svn: 133127
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