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authorEric Christopher <echristo@apple.com>2011-06-30 23:50:52 +0000
committerEric Christopher <echristo@apple.com>2011-06-30 23:50:52 +0000
commitcf2007ca785fa40dc4662256cea108728f812790 (patch)
treef6582ebe0ff77d2ae901930060569f0f26a4d4e4 /llvm/lib/Target/ARM/ARMISelLowering.cpp
parent40cc749788c7c55c2a983c8387cc471933a758b0 (diff)
downloadbcm5719-llvm-cf2007ca785fa40dc4662256cea108728f812790.tar.gz
bcm5719-llvm-cf2007ca785fa40dc4662256cea108728f812790.zip
Rename Pair to RCPair lacking any better naming ideas.
llvm-svn: 134210
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp20
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1b9bcc99660..09e1cc8dad4 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7528,8 +7528,8 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
return weight;
}
-typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
-Pair
+typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
+RCPair
ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const {
if (Constraint.size() == 1) {
@@ -7537,23 +7537,23 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
switch (Constraint[0]) {
case 'l': // Low regs or general regs.
if (Subtarget->isThumb())
- return Pair(0U, ARM::tGPRRegisterClass);
+ return RCPair(0U, ARM::tGPRRegisterClass);
else
- return Pair(0U, ARM::GPRRegisterClass);
+ return RCPair(0U, ARM::GPRRegisterClass);
case 'h': // High regs or no regs.
if (Subtarget->isThumb())
- return Pair(0U, ARM::hGPRRegisterClass);
+ return RCPair(0U, ARM::hGPRRegisterClass);
else
- return Pair(0u, static_cast<const TargetRegisterClass*>(0));
+ return RCPair(0u, static_cast<const TargetRegisterClass*>(0));
case 'r':
- return Pair(0U, ARM::GPRRegisterClass);
+ return RCPair(0U, ARM::GPRRegisterClass);
case 'w':
if (VT == MVT::f32)
- return Pair(0U, ARM::SPRRegisterClass);
+ return RCPair(0U, ARM::SPRRegisterClass);
if (VT.getSizeInBits() == 64)
- return Pair(0U, ARM::DPRRegisterClass);
+ return RCPair(0U, ARM::DPRRegisterClass);
if (VT.getSizeInBits() == 128)
- return Pair(0U, ARM::QPRRegisterClass);
+ return RCPair(0U, ARM::QPRRegisterClass);
break;
}
}
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