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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* [ARM] Add OptMinSize to ARMSubtargetSam Parker2019-02-081-9/+12
* [opaque pointer types] Pass value type to GetElementPtr creation.James Y Knight2019-02-011-3/+5
* [ARM] Deduplicate table generated CC analysis codeReid Kleckner2019-01-281-2/+0
* Reapply "IR: Add fp operations to atomicrmw"Matt Arsenault2019-01-221-0/+3
* Revert r351778: IR: Add fp operations to atomicrmwChandler Carruth2019-01-221-3/+0
* IR: Add fp operations to atomicrmwMatt Arsenault2019-01-221-0/+3
* [ARM] Combine ands+lsls to lsls+lsrs for Thumb1.Eli Friedman2019-01-221-4/+60
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] ComputeKnownBits to handle extract vectorsDiogo N. Sampaio2019-01-071-0/+27
* [ARM] Always use the version of computeKnownBits that returns a value. NFCI.Simon Pilgrim2018-12-211-8/+5
* [ARM] Complete the Thumb1 shift+and->shift+shift transforms.Eli Friedman2018-12-201-7/+46
* ARM: use acquire/release instruction variants when available.Tim Northover2018-12-171-1/+2
* ARM: use target-specific SUBS node when combining cmp with cmov.Tim Northover2018-12-031-11/+20
* [ARM] Don't expand sdiv when optimising for minsizeSjoerd Meijer2018-11-301-0/+44
* [ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.Eli Friedman2018-11-071-0/+44
* [NFC] Rename minnan and maxnan to minimum and maximumThomas Lively2018-10-241-13/+13
* ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.Peter Collingbourne2018-10-241-0/+1
* ARM: handle checking aliases with out-of-bounds GEPsSaleem Abdulrasool2018-10-241-3/+5
* [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281)Simon Pilgrim2018-10-151-130/+26
* [ARM] Fix correctness checks in promoteToConstantPool.Eli Friedman2018-09-281-46/+15
* [ARM] Use preferred alignment for constants in promoteToConstantPool.Eli Friedman2018-09-281-1/+1
* [ARM] Share predecessor bookkeeping in CombineBaseUpdate. NFCI.Nirav Dave2018-09-251-2/+9
* [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IRAlex Bradbury2018-09-191-4/+6
* ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.Tim Northover2018-09-131-0/+7
* [MinGW] Move code for indicating "potentially not DSO local" into shouldAssum...Martin Storsjo2018-09-041-3/+2
* [MinGW] [ARM] Add stubs for potential automatic dllimported variablesMartin Storsjo2018-08-311-3/+8
* [ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.Eli Friedman2018-08-221-1/+3
* [ARM] Handle all-ones mask explicitly in targetShrinkDemandedConstant.Eli Friedman2018-08-221-4/+11
* [AArch64] Add Tiny Code Model for AArch64David Green2018-08-221-0/+2
* [SDAG] Remove the reliance on MI's allocation strategy forChandler Carruth2018-08-141-4/+2
* [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.Eli Friedman2018-08-141-3/+20
* Fix unused lambda capture warning from r339472.Eli Friedman2018-08-101-1/+1
* [ARM] Adjust AND immediates to make them cheaper to select.Eli Friedman2018-08-101-0/+77
* [ARM] FP16: support vector INT_TO_FP and FP_TO_INTSjoerd Meijer2018-08-081-7/+35
* [ARM] FP16: support the vector vmin and vmax variantsSjoerd Meijer2018-08-081-0/+12
* Remove trailing spaceFangrui Song2018-07-301-5/+5
* [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1.Eli Friedman2018-07-251-0/+81
* ARM: stop explicitly marking armv7k libcalls as hard-float. NFC.Tim Northover2018-07-181-7/+0
* [ARM] Treat cmn immediates as legal in isLegalICmpImmediate.Eli Friedman2018-07-101-4/+6
* [NEON] Fix combining of vldx_dup intrinsics with updating of base addressesIvan A. Kosarev2018-07-051-0/+6
* [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.Vadzim Dambrouski2018-07-021-2/+6
* [NEON] Support vldNq intrinsics in AArch32 (LLVM part)Ivan A. Kosarev2018-06-271-1/+7
* [NEON] Support VST1xN intrinsics in AArch32 mode (LLVM part)Ivan A. Kosarev2018-06-101-0/+24
* [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)Ivan A. Kosarev2018-06-021-0/+18
* Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)"Ivan A. Kosarev2018-06-021-18/+0
* [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)Ivan A. Kosarev2018-06-021-0/+18
* [ARM] Remove code handling ADDC/ADDE/SUBC/SUBEAmaury Sechet2018-05-301-30/+0
* [ARM] Enable SETCCCARRY lowering for Thumb1.Eli Friedman2018-05-291-3/+1
* ARM: be conservative when asked load/store alignment of weird type.Tim Northover2018-05-211-0/+4
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-9/+8
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