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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-08-08 07:20:15 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-08-08 07:20:15 +0000 |
| commit | b264944ed5aade774c89ad9d820037e4b02798f0 (patch) | |
| tree | 0ad35b1779d5ddf8eeccb8d2530f3f8249f10bc7 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | c9dca6df788529e2ef56dd526435521877d79323 (diff) | |
| download | bcm5719-llvm-b264944ed5aade774c89ad9d820037e4b02798f0.tar.gz bcm5719-llvm-b264944ed5aade774c89ad9d820037e4b02798f0.zip | |
[ARM] FP16: support the vector vmin and vmax variants
Differential Revision: https://reviews.llvm.org/D50238
llvm-svn: 339221
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ede276dd91b..63d6b35cc81 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1144,6 +1144,18 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal); setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal); setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal); + + if (Subtarget->hasFullFP16()) { + setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal); + setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); + setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal); + setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); + + setOperationAction(ISD::FMINNAN, MVT::v4f16, Legal); + setOperationAction(ISD::FMAXNAN, MVT::v4f16, Legal); + setOperationAction(ISD::FMINNAN, MVT::v8f16, Legal); + setOperationAction(ISD::FMAXNAN, MVT::v8f16, Legal); + } } // We have target-specific dag combine patterns for the following nodes: |
