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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* Fix MSVC "32-bit shift implicitly converted to 64 bits" warnings. NFCI.Simon Pilgrim2019-09-071-1/+1
* [ARM] Sink add/mul(shufflevector(insertelement())) for MVE instruction selectionSam Tebbs2019-09-061-10/+48
* [Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignmentGuillaume Chatelet2019-09-061-1/+2
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-1/+2
* [ARM] Add support for the s,j,x,N,O inline asm constraintsDavid Candler2019-09-051-3/+3
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-2/+2
* [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia...David Green2019-09-031-0/+9
* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-031-0/+46
* [ARM] Use MQPR not QPR for MVE registersDavid Green2019-09-021-3/+3
* [ARM] Remove MVE masked loads/storesDavid Green2019-09-011-31/+0
* [ARM] MVE Masked loads and storesDavid Green2019-08-291-0/+31
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-281-2/+2
* [TargetLowering] Add buildLegalVectorShuffle facility to help build legal shu...Amaury Sechet2019-08-281-5/+4
* Reapply: [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32Sam Tebbs2019-08-221-6/+7
* Revert r369626 "[ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32"Hans Wennborg2019-08-221-7/+6
* [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32Sam Tebbs2019-08-221-6/+7
* [TargetLowering] Remove optional arguments passing to makeLibCallShiva Chen2019-08-221-5/+9
* [ARM] Add support for MVE vaddvSam Tebbs2019-08-191-0/+3
* Reland "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-0/+44
* Revert "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-44/+0
* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-161-0/+44
* [ARM] Don't pretend we know how to generate MVE VLDnDavid Green2019-08-161-0/+6
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-57/+57
* [ARM] Add support for MVE pre and post inc loads and storesDavid Green2019-08-081-15/+106
* [ARM] MVE big endian loads/storesDavid Green2019-08-081-36/+12
* [ARM] Tighten up VLDRH.32 with low alignmentsDavid Green2019-08-081-3/+10
* [ARM] Expand CTPOP intrinsic for MVEOliver Cruickshank2019-08-071-0/+1
* AMDGPU: Correct behavior of f16 buffer loadsMatt Arsenault2019-08-051-2/+3
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-8/+8
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-031-5/+6
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-1/+1
* [ARM] Lower "(x<<c) > 0x80000000U" to "lsls" on Thumb1.Eli Friedman2019-07-311-0/+25
* [ARM] Transform compare of masked value to shift on Thumb1.Eli Friedman2019-07-311-0/+37
* [ARM] Better patterns for fp <> predicate vectorsDavid Green2019-07-281-4/+0
* [ARM] Rewrite how VCMP are lowered, using a single nodeDavid Green2019-07-241-104/+106
* [ARM] Disable MVE fptosi and friendsDavid Green2019-07-241-0/+4
* [ARM] Better OR's for MVE comparesDavid Green2019-07-241-0/+57
* [ARM] MVE floating point compares and selectsDavid Green2019-07-241-1/+13
* [ARM] MVE predicate register supportDavid Green2019-07-241-13/+307
* [ARM] MVE integer compares and selectsDavid Green2019-07-241-5/+48
* [ARM][LowOverheadLoops] Fix branch target codegenSam Parker2019-07-231-26/+157
* [ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green2019-07-231-16/+16
* [IPRA][ARM] Make use of the "returned" parameter attributeOliver Stannard2019-07-221-0/+6
* [ARM][DAGCOMBINE][FIX] PerformVMOVRRDCombineDiogo N. Sampaio2019-07-181-3/+5
* Fix parameter name comments using clang-tidy. NFC.Rui Ueyama2019-07-161-3/+3
* [ARM] MVE vector for 64bit typesDavid Green2019-07-151-0/+6
* [ARM] MVE Vector ShiftsDavid Green2019-07-151-5/+8
* [ARM] Adjust how NEON shifts are loweredDavid Green2019-07-151-115/+136
* [ARM] Add sign and zero extend patterns for MVEDavid Green2019-07-131-1/+1
* [ARM] MVE integer absDavid Green2019-07-131-0/+1
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