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path: root/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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* Use simple RegState::Define flag instead of getDefRegState(true).Bob Wilson2010-10-151-5/+5
| | | | llvm-svn: 116601
* When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomesJim Grosbach2010-10-151-2/+1
| | | | | | an explicit def. Make sure to capture that properly. rdar://8556556 llvm-svn: 116591
* Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudosJim Grosbach2010-10-141-0/+29
| | | | | | | and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. llvm-svn: 116534
* Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually beJim Grosbach2010-10-061-0/+26
| | | | | | pseudo instructions. llvm-svn: 115840
* When expanding ARM pseudo registers, copy the existing predicate operandsBob Wilson2010-09-161-9/+29
| | | | | | instead of using default predicates on the expanded instructions. llvm-svn: 114066
* Add missing break.Bob Wilson2010-09-161-0/+1
| | | | llvm-svn: 114048
* Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded afterBob Wilson2010-09-161-0/+50
| | | | | | | register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. llvm-svn: 114047
* Avoid warnings.Bob Wilson2010-09-141-2/+3
| | | | llvm-svn: 113857
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-3/+54
| | | | | | | register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! llvm-svn: 113818
* Switch all the NEON vld-lane and vst-lane instructions over to the newBob Wilson2010-09-131-160/+435
| | | | | | | pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table to record all the NEON load/store information. llvm-svn: 113812
* For double-spaced VLD3/VLD4 instructions, copy the explicit super-register useBob Wilson2010-09-091-5/+9
| | | | | | | operand from the pseudo instruction to the new instruction as an implicit use. This will preserve any other flags (e.g., kill) on the operand. llvm-svn: 113456
* Simplify copying over operands from pseudo NEON load/store instructions.Bob Wilson2010-09-091-30/+19
| | | | | | | | For VLD3/VLD4 with double-spaced registers, add the implicit use of the super register for both the instruction loading the even registers and the instruction loading the odd registers. llvm-svn: 113452
* Clean up a comment.Bob Wilson2010-09-081-2/+2
| | | | llvm-svn: 113442
* Finish converting the rest of the NEON VLD instructions to use pseudo-Bob Wilson2010-09-031-11/+63
| | | | | | | | | instructions prior to regalloc. Since it's getting a little close to the 2.8 branch deadline, I'll have to leave the rest of the instructions handled by the NEONPreAllocPass for now, but I didn't want to leave half of the VLD instructions converted and the other half not. llvm-svn: 112983
* Fill in a missing comment.Bob Wilson2010-09-021-2/+2
| | | | llvm-svn: 112826
* Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson2010-09-021-0/+114
| | | | | | after regalloc. llvm-svn: 112825
* Expand MOVi32imm in ARM mode after regalloc. This providesAnton Korobeynikov2010-08-301-2/+7
| | | | | | | scheduling opportunities (extra instruction can go in between MOVT / MOVW pair removing the stall). llvm-svn: 112546
* When expanding NEON VST pseudo instructions, if the original super-registerBob Wilson2010-08-301-4/+6
| | | | | | | | | | operand is killed, add it to the expanded instruction as an implicit kill operand instead of marking the individual subregs with kill flags. This should work better in general and also handles the case for VST3 where one of the subregs was not referenced in the expanded instruction and so was not marked killed. llvm-svn: 112494
* Use pseudo instructions for VST1 and VST2.Bob Wilson2010-08-281-2/+45
| | | | llvm-svn: 112357
* Use pseudo instructions for VST3.Bob Wilson2010-08-261-25/+54
| | | | llvm-svn: 112208
* Use pseudo instructions for VST1d64Q.Bob Wilson2010-08-261-0/+4
| | | | llvm-svn: 112170
* Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson2010-08-251-4/+98
| | | | | | | | | | | with the VST4 instructions. Until after register allocation, we want to represent sets of adjacent registers by a single super-register. These VST4 pseudo instructions have a single QQ or QQQQ source register operand. They get expanded to the real VST4 instructions with 4 separate D register operands. Once this conversion is complete, we'll be able to remove the NEONPreAllocPass and avoid some fragile and hacky code elsewhere. llvm-svn: 112108
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* prune #includes a little.Chris Lattner2010-07-201-1/+1
| | | | llvm-svn: 108929
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-4/+6
| | | | llvm-svn: 105350
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-4/+4
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Expand VMOVQQ into a pair of VMOVQ.Evan Cheng2010-05-131-0/+27
| | | | llvm-svn: 103684
* Fix some potential issues in the pseudo instruction expansion phase: copy ↵Evan Cheng2010-05-121-35/+61
| | | | | | implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. llvm-svn: 103667
* Remove a dead fixme.Evan Cheng2010-05-121-1/+0
| | | | llvm-svn: 103642
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101334
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-10/+23
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-0/+115
load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
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