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authorJim Grosbach <grosbach@apple.com>2010-06-02 21:53:11 +0000
committerJim Grosbach <grosbach@apple.com>2010-06-02 21:53:11 +0000
commit84511e1526f7f2d47cb1035d27487802e6f0666d (patch)
treec6089b9726c52a2a3644c980a14747984a7a05e8 /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
parent7db953e39611fc41110212a6e6c11d7742b345fe (diff)
downloadbcm5719-llvm-84511e1526f7f2d47cb1035d27487802e6f0666d.tar.gz
bcm5719-llvm-84511e1526f7f2d47cb1035d27487802e6f0666d.zip
Clean up 80 column violations. No functional change.
llvm-svn: 105350
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index c87f5d7c16a..9c62597b432 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -144,13 +144,15 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
MachineInstrBuilder Even =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VMOVQ))
- .addReg(EvenDst, getDefRegState(true) | getDeadRegState(DstIsDead))
- .addReg(EvenSrc, getKillRegState(SrcIsKill)));
+ .addReg(EvenDst,
+ getDefRegState(true) | getDeadRegState(DstIsDead))
+ .addReg(EvenSrc, getKillRegState(SrcIsKill)));
MachineInstrBuilder Odd =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VMOVQ))
- .addReg(OddDst, getDefRegState(true) | getDeadRegState(DstIsDead))
- .addReg(OddSrc, getKillRegState(SrcIsKill)));
+ .addReg(OddDst,
+ getDefRegState(true) | getDeadRegState(DstIsDead))
+ .addReg(OddSrc, getKillRegState(SrcIsKill)));
TransferImpOps(MI, Even, Odd);
MI.eraseFromParent();
Modified = true;
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