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| author | Bob Wilson <bob.wilson@apple.com> | 2010-09-16 00:31:02 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-09-16 00:31:02 +0000 |
| commit | 6b853c3ce38b9228f6b8c77157f6b5741e4a25ff (patch) | |
| tree | ea5de010996bf3a3bcaf2bcf2520b1e244433437 /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 8dc0b041062f4eeacad4655a976e05a430706d19 (diff) | |
| download | bcm5719-llvm-6b853c3ce38b9228f6b8c77157f6b5741e4a25ff.tar.gz bcm5719-llvm-6b853c3ce38b9228f6b8c77157f6b5741e4a25ff.zip | |
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
llvm-svn: 114047
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 79fcfe8d1c1..4a3402fff1d 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -640,6 +640,56 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { MI.eraseFromParent(); } + case ARM::VLDMQ: { + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VLDMD)); + unsigned OpIdx = 0; + // Grab the Q register destination. + bool DstIsDead = MI.getOperand(OpIdx).isDead(); + unsigned DstReg = MI.getOperand(OpIdx++).getReg(); + // Copy the addrmode4 operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Add the destination operands (D subregs). + unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); + unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) + .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); + // Add an implicit def for the super-register. + MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); + break; + } + + case ARM::VSTMQ: { + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::VSTMD)); + unsigned OpIdx = 0; + // Grab the Q register source. + bool SrcIsKill = MI.getOperand(OpIdx).isKill(); + unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); + // Copy the addrmode4 operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the predicate operands. + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Add the source operands (D subregs). + unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); + unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); + MIB.addReg(D0).addReg(D1); + if (SrcIsKill) + // Add an implicit kill for the Q register. + (*MIB).addRegisterKilled(SrcReg, TRI, true); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); + break; + } + case ARM::VLD1q8Pseudo: case ARM::VLD1q16Pseudo: case ARM::VLD1q32Pseudo: |
