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authorEvan Cheng <evan.cheng@apple.com>2010-05-13 00:17:02 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-05-13 00:17:02 +0000
commit2f736c9577748663371301278be92955af055a79 (patch)
treed277f07c2c8569aefb8804d2cfdd8772030817fc /llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
parent79efd71962f6d0ab61a7c8f4fe8bcdc36961b5f8 (diff)
downloadbcm5719-llvm-2f736c9577748663371301278be92955af055a79.tar.gz
bcm5719-llvm-2f736c9577748663371301278be92955af055a79.zip
Expand VMOVQQ into a pair of VMOVQ.
llvm-svn: 103684
Diffstat (limited to 'llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp27
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 7907905a0f2..1b6ce4e173a 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -29,6 +29,7 @@ namespace {
ARMExpandPseudo() : MachineFunctionPass(&ID) {}
const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI;
virtual bool runOnMachineFunction(MachineFunction &Fn);
@@ -128,6 +129,31 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
TransferImpOps(MI, LO16, HI16);
MI.eraseFromParent();
Modified = true;
+ break;
+ }
+
+ case ARM::VMOVQQ: {
+ unsigned DstReg = MI.getOperand(0).getReg();
+ bool DstIsDead = MI.getOperand(0).isDead();
+ unsigned EvenDst = TRI->getSubReg(DstReg, ARM::QSUBREG_0);
+ unsigned OddDst = TRI->getSubReg(DstReg, ARM::QSUBREG_1);
+ unsigned SrcReg = MI.getOperand(1).getReg();
+ bool SrcIsKill = MI.getOperand(1).isKill();
+ unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_0);
+ unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_1);
+ MachineInstrBuilder Even =
+ AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+ TII->get(ARM::VMOVQ))
+ .addReg(EvenDst, getDefRegState(true) | getDeadRegState(DstIsDead))
+ .addReg(EvenSrc, getKillRegState(SrcIsKill)));
+ MachineInstrBuilder Odd =
+ AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+ TII->get(ARM::VMOVQ))
+ .addReg(OddDst, getDefRegState(true) | getDeadRegState(DstIsDead))
+ .addReg(OddSrc, getKillRegState(SrcIsKill)));
+ TransferImpOps(MI, Even, Odd);
+ MI.eraseFromParent();
+ Modified = true;
}
}
MBBI = NMBBI;
@@ -138,6 +164,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getTarget().getInstrInfo();
+ TRI = MF.getTarget().getRegisterInfo();
bool Modified = false;
for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
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