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* Add a -arm-align-constant-islands flag, default off.Jakob Stoklund Olesen2011-12-121-9/+35
| | | | | | | | | | | | Order constant pool entries by descending alignment in the initial island to ensure packing and correct alignment. When the command line flag is set, also align the basic block containing the constant pool entries. This is only a partial implementation of constant island alignment. More to come. llvm-svn: 146375
* Try to align the point where a large basic block is split.Jakob Stoklund Olesen2011-12-101-11/+50
| | | | | | | | | | | | | | | | The split point is picked such that the newly created water has the same alignment as the function. This makes the island suitable for constant pool entries with potentially higher alignment. This also fixes an issue where the basic block was split one instruction too late, causing nonconvergence of the algorithm. <rdar://problem/10550705> There is still an issue with correctly packing differently aligned entries in the island. llvm-svn: 146314
* More debug output formatting.Jakob Stoklund Olesen2011-12-101-9/+20
| | | | llvm-svn: 146313
* User a helper overload for a common pattern.Jakob Stoklund Olesen2011-12-091-8/+11
| | | | llvm-svn: 146270
* Tweak debugging output.Jakob Stoklund Olesen2011-12-091-20/+28
| | | | llvm-svn: 146264
* Drop the HasInlineAsm flag.Jakob Stoklund Olesen2011-12-081-8/+2
| | | | | | | | | | It is not used any more. We are tracking inline assembly misalignments directly through the BBInfo.Unalign and KnownBits fields. A simple conservative size estimate is not good enough since it can cause alignment padding to be underestimated. llvm-svn: 146124
* Simplify offset verification.Jakob Stoklund Olesen2011-12-081-9/+4
| | | | llvm-svn: 146121
* Don't include alignment padding in BBInfo.Size.Jakob Stoklund Olesen2011-12-081-145/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | Compute alignment padding before and after basic blocks dynamically. Heed basic block alignment. This simplifies bookkeeping because we don't have to constantly add and remove padding from BBInfo.Size. It also makes it possible to track the extra known alignment bits we get after a tBR_JTr terminator and when entering an aligned basic block. This makes the ARMConstantIslandPass aware of aligned basic blocks. It is tricky to model block alignment correctly when dealing with inline assembly and tBR_JTr instructions that have variable size. If inline assembly turns out to be smaller than expected, that may cause following alignment padding to be larger than expected. This could cause constant pool entries to move out of range. To avoid that problem, we use the worst case alignment padding following inline assembly. This may cause slightly suboptimal constant island placement in aligned basic blocks following inline assembly. Normal functions should be unaffected. llvm-svn: 146118
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Eliminate delta argument from AdjustBBOffsetsAfter.Jakob Stoklund Olesen2011-12-071-24/+15
| | | | | | | | | The block offset can be computed from the previous block. That is more robust than keeping track of a delta. Eliminate one redundant AdjustBBOffsetsAfter call. llvm-svn: 146018
* Compute some alignment information for each basic block.Jakob Stoklund Olesen2011-12-071-14/+48
| | | | | | These fields are not used for anything yet. llvm-svn: 146017
* Move common expression into a method.Jakob Stoklund Olesen2011-12-071-10/+10
| | | | llvm-svn: 146008
* Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.Jakob Stoklund Olesen2011-12-071-74/+78
| | | | | | No functional change is intended. llvm-svn: 146005
* Revert r145971: "Use conservative size estimate for tBR_JTr."Jakob Stoklund Olesen2011-12-061-1/+23
| | | | | | This caused more offset errors. llvm-svn: 145980
* Use conservative size estimate for tBR_JTr.Jakob Stoklund Olesen2011-12-061-23/+1
| | | | | | | | | | This pseudo-instruction contains a .align directive in its expansion, so the total size may vary by 2 bytes. It is too difficult to accurately keep track of this alignment directive, just use the worst-case size instead. llvm-svn: 145971
* Remove alignment from deserted constant islands.Jakob Stoklund Olesen2011-12-061-0/+3
| | | | | | | | | | | | | | | | ARMConstantIslandPass may sometimes leave empty constant islands behind (it really shouldn't). Remove the alignment from the empty islands so the size calculations are still correct. This should fix the many Thumb1 assembler errors in the nightly test suite. The reduced test case for this problem is way too big. That is to be expected for ARMConstantIslandPass bugs. <rdar://problem/10534709> llvm-svn: 145970
* Align ARM constant pool islands via their basic block.Jakob Stoklund Olesen2011-12-061-0/+6
| | | | | | | | | | | Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. llvm-svn: 145890
* Use an existing function.Jakob Stoklund Olesen2011-12-061-10/+1
| | | | llvm-svn: 145883
* There's no need to add additional predicate operands when converting a tB to ↵Owen Anderson2011-09-121-2/+0
| | | | | | a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404> llvm-svn: 139531
* Fix buildbot breakage caused by r139415. I missed one instance of a ↵Owen Anderson2011-09-091-1/+5
| | | | | | manually create ARM::tB. llvm-svn: 139429
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-3/+12
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Re-apply r135319 with a fix for the constant island pass.Owen Anderson2011-07-181-0/+2
| | | | | | Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. llvm-svn: 135414
* Make tBX_RET and tBX_RET_vararg predicable.Jim Grosbach2011-07-081-1/+4
| | | | | | | | | | The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. llvm-svn: 134746
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-6/+6
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Avoid de-referencing pass beginning of a basic block. No small test case ↵Evan Cheng2011-04-011-18/+21
| | | | | | possible. rdar://9216009 llvm-svn: 128743
* Spelling fix: consequtive -> consecutive.Duncan Sands2011-02-151-1/+1
| | | | llvm-svn: 125563
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-19/+1
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-081-0/+14
| | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. llvm-svn: 125074
* Save a mapping between original and cloned constpool entries.Anton Korobeynikov2011-01-301-0/+8
| | | | llvm-svn: 124570
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-2/+2
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Comment cleanups.Bill Wendling2010-12-211-2/+2
| | | | llvm-svn: 122302
* RemoveUnusedCPEntries can change things. Track it.Bill Wendling2010-12-181-1/+1
| | | | llvm-svn: 122129
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-151-1/+0
| | | | | | Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-5/+5
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-5/+5
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-071-1/+1
| | | | | | | possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-1/+5
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-1/+1
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Remove extra header.Eric Christopher2010-08-181-1/+0
| | | | llvm-svn: 111456
* Make sure ARM constant island pass does not break up an IT block. If the ↵Evan Cheng2010-08-121-3/+20
| | | | | | split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 llvm-svn: 110947
* Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable ↵Evan Cheng2010-08-091-1/+1
| | | | | | more 32-bit to 16-bit optimizations. llvm-svn: 110584
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Revert 109076. It is wrong and was causing regressions. Add someDale Johannesen2010-07-231-18/+48
| | | | | | | | | | comments explaining why it was wrong. 8225024. Fix the real problem in 8213383: the code that splits very large blocks when no other place to put constants can be found was not considering the case that the block contained a Thumb tablejump. llvm-svn: 109282
* eliminate the TargetInstrInfo::GetInstSizeInBytes hook. Chris Lattner2010-07-221-2/+2
| | | | | | | | ARM/PPC/MSP430-specific code (which are the only targets that implement the hook) can directly reference their target-specific instrinfo classes. llvm-svn: 109171
* Fix constant island pass's handling of tBR_JTr. The offset of the ↵Evan Cheng2010-07-221-2/+10
| | | | | | | | | | | | | instruction does not have to be 4-byte aligned. Rather, it's the offset + 2 that must be aligned since the instruction expands into: mov pc, r1 .align 2 LJTI0_0_0: .long LBB0_14 This fixes rdar://8213383. No test case since it's not possible to come up with a suitable small one. llvm-svn: 109076
* grammarJim Grosbach2010-07-071-1/+1
| | | | llvm-svn: 107831
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