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authorOwen Anderson <resistor@mac.com>2010-12-13 22:51:08 +0000
committerOwen Anderson <resistor@mac.com>2010-12-13 22:51:08 +0000
commit9a4d42855d2f21239332e69ecb3cfdd1524b9738 (patch)
treebc3e1b774512cf44c9bb3a029d15281a3e31820c /llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
parentc4bf5cac9fe8b68b755fc07d6890e443ba594dd3 (diff)
downloadbcm5719-llvm-9a4d42855d2f21239332e69ecb3cfdd1524b9738.tar.gz
bcm5719-llvm-9a4d42855d2f21239332e69ecb3cfdd1524b9738.zip
Revert r121721, which broke buildbots.
llvm-svn: 121726
Diffstat (limited to 'llvm/lib/Target/ARM/ARMConstantIslandPass.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMConstantIslandPass.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 9434ecf40bd..8066cb735b1 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -594,7 +594,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
NegOk = true;
IsSoImm = true;
break;
- case ARM::t2ADR:
+ case ARM::t2LEApcrel:
Bits = 12;
NegOk = true;
break;
@@ -1555,7 +1555,7 @@ bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
unsigned Bits = 0;
switch (Opcode) {
default: break;
- case ARM::t2ADR:
+ case ARM::t2LEApcrel:
if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
NewOpc = ARM::tLEApcrel;
Bits = 8;
@@ -1754,16 +1754,16 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
if (!OptOk)
continue;
- // Now scan back again to find the tLEApcrel or t2ADR instruction
+ // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
// that gave us the initial base register definition.
for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
;
- // The instruction should be a tLEApcrel or t2ADR; we want
+ // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
// to delete it as well.
MachineInstr *LeaMI = PrevI;
if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
- LeaMI->getOpcode() != ARM::t2ADR) ||
+ LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
LeaMI->getOperand(0).getReg() != BaseReg)
OptOk = false;
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