Temporary workaround for a bad bug introduced by r121082 which replaced

t2LDRpci with t2LDRi12.
There are a couple of problems with this.
1. The encoding for the literal and immediate constant are different.
   Note bit 7 of the literal case is 'U' so it can be negative.
2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run.
   So we end up never using the Thumb2 instruction, which ends up creating a
   lot more constant islands.

llvm-svn: 125074

1 files changed, 14 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index dd81796e8aa..f8f717e4d4a 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1576,6 +1576,16 @@ bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
         Scale = 4;
       }
       break;
+    case ARM::t2LDRi12:
+      // FIXME: Temporary workaround for a  bug introduced by r121082.
+      // We should use t2LDRpci for loads from constantpools.
+      if (isARMLowRegister(U.MI->getOperand(0).getReg()) &&
+          U.MI->getOperand(1).getReg() == ARM::PC) {
+        NewOpc = ARM::tLDRpci;
+        Bits = 8;
+        Scale = 4;
+      }
+      break;
     }
 
     if (!NewOpc)
@@ -1586,6 +1596,10 @@ bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
     // FIXME: Check if offset is multiple of scale if scale is not 4.
     if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
       U.MI->setDesc(TII->get(NewOpc));
+      if (NewOpc == ARM::tLDRpci)
+        // FIXME: Temporary workaround.
+        // PC is now an implicit operand.
+        U.MI->RemoveOperand(1);
       MachineBasicBlock *MBB = U.MI->getParent();
       BBSizes[MBB->getNumber()] -= 2;
       AdjustBBOffsetsAfter(MBB, -2);