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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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* [ARM] Cortex-A57 scheduling model for ARM backend (AArch32)Javed Absar2017-06-021-0/+18
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-14/+4
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-4/+0
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-0/+4
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-211-4/+0
* ARM: Use methods to access data stored with frame instructionsSerge Pavlov2017-04-191-0/+23
* TargetInstrInfo: Provide default implementation of isTailCall().Matthias Braun2017-03-161-2/+0
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-1/+1
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ...Eugene Zelenko2017-01-311-8/+13
* [XRay][Arm32] Reduce the portion of the stub and implement more staging for t...Serge Rogatch2017-01-261-0/+2
* [ARM] CodeGen: Replace AddDefaultT1CC and AddNoT1CC. NFCDiana Picus2017-01-131-11/+7
* [ARM] CodeGen: Remove AddDefaultCC. NFC.Diana Picus2017-01-131-5/+5
* [ARM] CodeGen: Remove AddDefaultPred. NFC.Diana Picus2017-01-131-3/+10
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-191-0/+4
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-1/+1
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-2/+4
* Revert "[XRay] ARM 32-bit no-Thumb support in LLVM"Renato Golin2016-09-081-4/+0
* [XRay] ARM 32-bit no-Thumb support in LLVMDean Michael Berris2016-09-081-0/+4
* Fix for commit rL277126 that broke a build.Sjoerd Meijer2016-07-291-1/+1
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-1/+1
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-1/+1
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-37/+43
* Don't pass Reloc::Model to places that already have it. NFC.Rafael Espindola2016-06-281-4/+2
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-10/+13
* CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith2016-02-231-10/+10
* [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.Scott Douglass2015-10-051-0/+2
* Improved the interface of methods commuting operands, improved X86-FMA3 mem-f...Andrew Kaylor2015-09-281-3/+12
* Pass BranchProbability/BlockMass by value instead of const& as they are small...Cong Hou2015-09-101-3/+3
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
* MachineLICM: Use TargetSchedModel instead of just itinerariesMatthias Braun2015-06-131-2/+2
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-111-5/+4
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-181-1/+1
* Peephole opt needs optimizeSelect() to keep track of newly created MIsMehdi Amini2015-01-131-1/+3
* Add Forward Control-Flow Integrity.Tom Roeder2014-11-111-6/+0
* ARM: allow copying of CPSR when all else fails.Tim Northover2014-10-011-0/+7
* [ARM] Move the implementation of the target hooks related to copy-relatedQuentin Colombet2014-08-221-0/+47
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-0/+8
* The hazard recognizer only needs a subtarget, not a target machineEric Christopher2014-06-131-1/+1
* Add a new attribute called 'jumptable' that creates jump-instruction tables f...Tom Roeder2014-06-051-0/+7
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
* Prune includes in ARM target.Craig Topper2014-03-221-1/+1
* [C++11] Add 'override' keyword to virtual methods that override their base cl...Craig Topper2014-03-101-113/+109
* ARM: decide whether to use movw/movt based on "minsize" attribute.Tim Northover2013-12-021-1/+2
* ARM: fold prologue/epilogue sp updates into push/pop for code sizeTim Northover2013-11-081-0/+18
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+2
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-161-6/+0
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
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