summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Enable predication of NEON instructions in Thumb2 mode.Evan Cheng2009-11-241-5/+1
| | | | llvm-svn: 89748
* Add predicate operand to NEON instructions. Fix lots (but not all) 80 col ↵Evan Cheng2009-11-211-12/+35
| | | | | | violations in ARMInstrNEON.td. llvm-svn: 89542
* Also CSE non-pic load from constant pools.Evan Cheng2009-11-201-1/+4
| | | | llvm-svn: 89440
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-181-0/+10
| | | | | | | | | contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. llvm-svn: 89187
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-0/+1
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* set the def of the VLD1q64 properlyJim Grosbach2009-11-151-2/+1
| | | | llvm-svn: 88873
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-1/+8
| | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-21/+21
| | | | llvm-svn: 86494
* Use aligned load/store instructions for spilling Q registers when we know ↵Jim Grosbach2009-11-081-6/+23
| | | | | | the stack slot is 128 bit aligned llvm-svn: 86425
* Refactor code.Evan Cheng2009-11-081-0/+54
| | | | llvm-svn: 86423
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-1/+1
| | | | llvm-svn: 86408
* Refactor code. Fix a potential missing check. Teach isIdentical() about ↵Evan Cheng2009-11-071-0/+33
| | | | | | tLDRpci_pic. llvm-svn: 86330
* Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So ↵Evan Cheng2009-11-031-1/+1
| | | | | | it should be 22 bytes instead of 20 bytes long. llvm-svn: 85965
* Trim unnecessary include.Evan Cheng2009-11-031-1/+0
| | | | llvm-svn: 85878
* Clean up copyRegToReg.Evan Cheng2009-11-031-27/+13
| | | | llvm-svn: 85870
* Turn neon reg-reg moves fixup code into separate pass. This should reduce ↵Anton Korobeynikov2009-11-031-33/+2
| | | | | | the compile time. llvm-svn: 85850
* Unbreak ARMBaseRegisterInfo::copyRegToReg.Evan Cheng2009-11-021-18/+19
| | | | llvm-svn: 85787
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" ↵Anton Korobeynikov2009-11-021-8/+46
| | | | | | stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) llvm-svn: 85764
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-1/+2
| | | | | | | opcode and operand with a tab. Check for these instructions in the usual places. llvm-svn: 85411
* Don't forget subreg indices when folding load / store.Evan Cheng2009-10-251-10/+30
| | | | llvm-svn: 85048
* 80 col violation.Evan Cheng2009-10-241-1/+2
| | | | llvm-svn: 84986
* -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixedEvan Cheng2009-10-181-8/+2
| | | | | | | | | | | stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. llvm-svn: 84424
* Distinquish stack slots from other stack objects. They (and fixed objects) ↵Evan Cheng2009-10-171-2/+8
| | | | | | get FixedStack PseudoSourceValues. llvm-svn: 84326
* Revert 84315 for now. Re-thinking the patch.Evan Cheng2009-10-171-2/+2
| | | | llvm-svn: 84321
* Rename getFixedStack to getStackObject. The stack objects represented are notEvan Cheng2009-10-171-2/+2
| | | | | | necessarily fixed. Only those will negative frame indices are "fixed." llvm-svn: 84315
* Add PseudoSourceValues for constpool stuff on ELF (Darwin should use ↵Anton Korobeynikov2009-10-071-8/+26
| | | | | | | | something similar) and register spills. llvm-svn: 83435
* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-0/+1
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. llvm-svn: 83006
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-1/+2
| | | | | | | | | instruction. This makes it re-materializable. Thumb2 will split it back out into two instructions so IT pass will generate the right mask. Also, this expose opportunies to optimize the movw to a 16-bit move. llvm-svn: 82982
* Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed toAnton Korobeynikov2009-09-121-3/+11
| | | | | | constraint the register usage. llvm-svn: 81635
* Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails andAnton Korobeynikov2009-09-081-10/+25
| | | | | | makes the code faster. llvm-svn: 81220
* Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which ↵Evan Cheng2009-08-271-8/+13
| | | | | | cannot fold any immediate offset. llvm-svn: 80191
* rename TAI -> MAI, being careful not to make MAILJMP instructions :)Chris Lattner2009-08-221-2/+2
| | | | llvm-svn: 79777
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-2/+2
| | | | llvm-svn: 79763
* Record variable debug info at ISel time directly.Devang Patel2009-08-221-1/+0
| | | | llvm-svn: 79742
* Add Thumb2 eh_sjlj_setjmp implementationJim Grosbach2009-08-111-0/+2
| | | | llvm-svn: 78701
* fix GetInstSizeInBytes for eh_sjlj_setjmpJim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78683
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-5/+5
| | | | llvm-svn: 78666
* Add support for folding loads / stores into 16-bit moves used by Thumb2.Evan Cheng2009-08-101-37/+61
| | | | llvm-svn: 78558
* 80 col violation.Evan Cheng2009-08-101-2/+3
| | | | llvm-svn: 78557
* Use VLDM / VSTM to spill/reload 128-bit Neon registersAnton Korobeynikov2009-08-081-4/+13
| | | | llvm-svn: 78468
* Code refactoring. No functionality change.Evan Cheng2009-08-081-0/+16
| | | | llvm-svn: 78455
* Fix support to use NEON for single precision fp math.Evan Cheng2009-08-071-5/+7
| | | | llvm-svn: 78397
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-1/+1
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
* When using NEON for single-precision FP, the NEON result must be placed in ↵David Goodwin2009-08-051-7/+13
| | | | | | D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. llvm-svn: 78244
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-2/+2
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-011-3/+8
| | | | llvm-svn: 77781
* t2BR_JT is mov pc, it's 2 byte long, not 4.Evan Cheng2009-07-311-9/+9
| | | | llvm-svn: 77744
* - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offsetEvan Cheng2009-07-311-3/+8
| | | | | | | is scaled by two. - Teach GetInstSizeInBytes about TBB and TBH. llvm-svn: 77701
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-7/+151
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* convertToThreeAddress can't handle Thumb2 instructions (which don't have ↵Evan Cheng2009-07-271-10/+7
| | | | | | same address mode as ARM instructions). llvm-svn: 77230
OpenPOWER on IntegriCloud