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| author | Evan Cheng <evan.cheng@apple.com> | 2009-08-07 19:30:41 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-07 19:30:41 +0000 |
| commit | 4c3b1ca5a0cc0ffde7afe7e2d8d1d4623559b0cc (patch) | |
| tree | dcda5365505901b8b61842ba85924ef53734f873 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | c266c6d797f74090266fb8812029f92a34fb5151 (diff) | |
| download | bcm5719-llvm-4c3b1ca5a0cc0ffde7afe7e2d8d1d4623559b0cc.tar.gz bcm5719-llvm-4c3b1ca5a0cc0ffde7afe7e2d8d1d4623559b0cc.zip | |
Fix support to use NEON for single precision fp math.
llvm-svn: 78397
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 911b84dc7de..ae28ccbb2de 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -587,7 +587,7 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, } break; case ARM::FSTD: - case ARM::FSTS: + case ARM::FSTS: if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) { @@ -610,8 +610,10 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, if (I != MBB.end()) DL = I->getDebugLoc(); if (DestRC != SrcRC) { - if (((DestRC == ARM::DPRRegisterClass) && (SrcRC == ARM::DPR_VFP2RegisterClass)) || - ((SrcRC == ARM::DPRRegisterClass) && (DestRC == ARM::DPR_VFP2RegisterClass))) { + if (((DestRC == ARM::DPRRegisterClass) && + (SrcRC == ARM::DPR_VFP2RegisterClass)) || + ((SrcRC == ARM::DPRRegisterClass) && + (DestRC == ARM::DPR_VFP2RegisterClass))) { // Allow copy between DPR and DPR_VFP2. } else { return false; @@ -648,7 +650,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addReg(0).addImm(0)); - } else if (RC == ARM::DPRRegisterClass) { + } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0)); @@ -670,7 +672,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (RC == ARM::GPRRegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) .addFrameIndex(FI).addReg(0).addImm(0)); - } else if (RC == ARM::DPRRegisterClass) { + } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) .addFrameIndex(FI).addImm(0)); } else { |
