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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-09-12 22:21:08 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-09-12 22:21:08 +0000 |
| commit | 8d0fbebb9ff87765a1eef07b11b6f48f3ce81b48 (patch) | |
| tree | 3bfe47dcbe0a7eab2a32dabe4499e33003d3a549 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | f436e878137edbeaaf792649a68f0c9a432d1cb1 (diff) | |
| download | bcm5719-llvm-8d0fbebb9ff87765a1eef07b11b6f48f3ce81b48.tar.gz bcm5719-llvm-8d0fbebb9ff87765a1eef07b11b6f48f3ce81b48.zip | |
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.
llvm-svn: 81635
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9da847a5762..52af9786954 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -613,6 +613,7 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, if (DestRC != SrcRC) { // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies + // Allow QPR / QPR_VFP2 cross-class copies if (DestRC == ARM::DPRRegisterClass) { if (SrcRC == ARM::DPR_VFP2RegisterClass || SrcRC == ARM::DPR_8RegisterClass) { @@ -628,6 +629,10 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, SrcRC == ARM::DPR_VFP2RegisterClass) { } else return false; + } else if ((DestRC == ARM::QPRRegisterClass && + SrcRC == ARM::QPR_VFP2RegisterClass) || + (DestRC == ARM::QPR_VFP2RegisterClass && + SrcRC == ARM::QPRRegisterClass)) { } else return false; } @@ -643,7 +648,8 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, (DestRC == ARM::DPR_8RegisterClass)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); - } else if (DestRC == ARM::QPRRegisterClass) { + } else if (DestRC == ARM::QPRRegisterClass || + DestRC == ARM::QPR_VFP2RegisterClass) { BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); } else { return false; @@ -674,7 +680,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0)); } else { - assert(RC == ARM::QPRRegisterClass && "Unknown regclass!"); + assert((RC == ARM::QPRRegisterClass || + RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); // FIXME: Neon instructions should support predicates BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0); @@ -700,7 +707,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) .addFrameIndex(FI).addImm(0)); } else { - assert(RC == ARM::QPRRegisterClass && "Unknown regclass!"); + assert((RC == ARM::QPRRegisterClass || + RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); // FIXME: Neon instructions should support predicates BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0); } |
