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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-10/+2
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-5/+5
| | | | llvm-svn: 105350
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-1/+2
| | | | llvm-svn: 105344
* Update the saved stack pointer in the sjlj function context following eitherJim Grosbach2010-05-271-2/+2
| | | | | | an alloca() or an llvm.stackrestore(). rdar://8031573 llvm-svn: 104900
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-32/+32
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-0/+37
| | | | llvm-svn: 104421
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-221-0/+4
| | | | | | | Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-13/+41
| | | | llvm-svn: 103760
* Bring back VLD1q and VST1q and use them for reloading / spilling Q ↵Evan Cheng2010-05-131-29/+69
| | | | | | registers. This allows folding loads and stores into VMOVQ. llvm-svn: 103692
* Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack ↵Evan Cheng2010-05-071-5/+39
| | | | | | slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. llvm-svn: 103235
* Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / ↵Evan Cheng2010-05-071-9/+15
| | | | | | VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. llvm-svn: 103234
* Remove VLD1q and VST1q for reloading and spilling Q registers. Just use ↵Evan Cheng2010-05-071-9/+23
| | | | | | VLD1q64 / VST1q64 and reference sub-registers. llvm-svn: 103218
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-4/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng2010-05-061-16/+35
| | | | | | coalescer bug that's fixed by 103170. llvm-svn: 103172
* Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.Dan Gohman2010-05-061-4/+2
| | | | llvm-svn: 103163
* Revert r103156 since it was breaking the build bots.Eric Christopher2010-05-061-31/+14
| | | | | | | | | | | Reverse-merging r103156 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMRegisterInfo.h U lib/Target/ARM/ARMBaseRegisterInfo.cpp U lib/Target/ARM/ARMBaseInstrInfo.cpp U lib/Target/ARM/ARMRegisterInfo.td llvm-svn: 103159
* Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103157
* Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q ↵Evan Cheng2010-05-061-14/+31
| | | | | | registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. llvm-svn: 103156
* Cosmetic changes.Evan Cheng2010-05-061-7/+7
| | | | llvm-svn: 103155
* storeRegToStackSlot has forgotten about QPR_8 register class.Evan Cheng2010-05-061-1/+2
| | | | llvm-svn: 103154
* Frame index can be negative.Evan Cheng2010-04-291-1/+1
| | | | llvm-svn: 102577
* Add sizes non-floating point versions for the eh sjlj intrinsic expansions.Jim Grosbach2010-04-281-1/+2
| | | | | | rdar://7895451 llvm-svn: 102526
* Add ARM specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+10
| | | | llvm-svn: 102324
* Educate GetInstrSizeInBytes implementations thatDale Johannesen2010-04-071-0/+1
| | | | | | DBG_VALUE does not generate code. llvm-svn: 100681
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-4/+4
| | | | llvm-svn: 100214
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-1/+14
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.Bob Wilson2010-03-231-2/+6
| | | | | | | | | | These instructions are only needed for codegen, so I've removed all the explicit encoding bits for now; they should be set in the same way as the for VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5 requires that the instructions be custom-selected so that the number of registers can be set in the AM5Opc value. llvm-svn: 99309
* Rename some instructions to match the corresponding NEON opcode.Bob Wilson2010-03-231-2/+2
| | | | llvm-svn: 99266
* Change VST1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-1/+1
| | | | | | | of D registers. Add a separate VST1q instruction with a Q register source operand for use by storeRegToStackSlot. llvm-svn: 99265
* Change VLD1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-1/+1
| | | | | | | of D registers. Add a separate VLD1q instruction with a Q register destination operand for use by loadRegFromStackSlot. llvm-svn: 99261
* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-4/+3
| | | | | | | with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
* Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass ↵Anton Korobeynikov2010-03-181-29/+39
| | | | | | copies weirdness more straightforward. Also, add GPR <-> SPR copy support. llvm-svn: 98887
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-161-3/+4
| | | | llvm-svn: 98692
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-161-4/+3
| | | | | | | optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. llvm-svn: 98683
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-031-4/+3
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Handle tGPR register class in a few more places. This fixes some llvm-gccBob Wilson2010-02-161-0/+10
| | | | | | build failures due to my fix for pr6111. llvm-svn: 96402
* Fix pr6111: Avoid using the LR register for the target address of an indirectBob Wilson2010-02-161-0/+7
| | | | | | | | branch in ARM v4 code, since it gets clobbered by the return address before it is used. Instead of adding a new register class containing all the GPRs except LR, just use the existing tGPR class. llvm-svn: 96360
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-4/+4
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* tighten up eh.setjmp sequence a bit.Jim Grosbach2010-02-081-2/+2
| | | | llvm-svn: 95603
* Adjust setjmp instruction sequence to not need 32-bit alignment paddingJim Grosbach2010-01-271-1/+1
| | | | llvm-svn: 94627
* prep work to support a future where getJumpTableInfo will returnChris Lattner2010-01-251-0/+1
| | | | | | | a null pointer for functions with no jump tables. No functionality change. llvm-svn: 94469
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-2/+2
| | | | | | | | | | | function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. llvm-svn: 93885
* Add Target hook to duplicate machine instructions.Jakob Stoklund Olesen2010-01-061-21/+46
| | | | | | | Some instructions refer to unique labels, and so cannot be trivially cloned with CloneMachineInstr. llvm-svn: 92873
* Remove dead variable.Bill Wendling2009-12-281-2/+0
| | | | llvm-svn: 92193
* remove out of date FIXME.Jim Grosbach2009-12-031-1/+0
| | | | llvm-svn: 90490
* fix a build problem with VC++, PR5664, patch by Alp Toker!Chris Lattner2009-12-031-2/+4
| | | | llvm-svn: 90419
* Thumb1 exception handling setjmpJim Grosbach2009-12-011-0/+2
| | | | llvm-svn: 90246
* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-301-6/+0
| | | | | | | | | for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. llvm-svn: 90144
* Refactor target hook for tail duplication as requested by Chris.Bob Wilson2009-11-241-6/+2
| | | | | | | | | | | | Make tail duplication of indirect branches much more aggressive (for targets that indicate that it is profitable), based on further experience with this transformation. I compiled 3 large applications with and without this more aggressive tail duplication and measured minimal changes in code size. ("size" on Darwin seems to round the text size up to the nearest page boundary, so I can only say that any code size increase was less than one 4k page.) Radar 7421267. llvm-svn: 89814
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